1 ? 2003 integrated device technology, inc. all rights reserved. dsc-6221/5 quad channel t1/e 1/j1 long haul/ short haul line interface unit idt82v2084 features: ? four channel t1/e1/j1 long ha ul/short haul line interfaces ? supports hps (hitless protection switching) for 1+1 protection without external relays ? receiver sensitivity exceeds -36 db@772khz and -43 db@1024 khz ? programmable t1/e1/j1 switchab ility allowing one bill of ma- terial for any line condition ? single 3.3 v power supply with 5 v tolerance on digital interfaces ? meets or exceeds specifications in - ansi t1.102, t1.403 and t1.408 - itu i.431, g.703,g.736, g.775 and g.823 - etsi 300-166, 300-233 and tbr 12/13 - at&t pub 62411 ? per channel software selectable on: - wave-shaping templates for short haul and long haul lbo (line build out) - line terminating impedance (t1:100 ? , j1:110 ?, e1:75 ?/ 120 ?) - adjustment of arbitrary pulse shape - ja (jitter attenuator) position (receive path or transmit path) - single rail/dual rail system interfaces - b8zs/hdb3/ami line encoding/decoding - active edge of transmit clock (tclk) and receive clock (rclk) - active level of transmit dat a (tdata) and receive data (rdata) - receiver or transmitter power down - high impedance setting for line drivers - prbs (pseudo random bit sequence) generation and detection with 2 15 -1 prbs polynomials for e1 - qrss (quasi random sequence si gnals) generation and detection with 2 20 -1 qrss polynomials for t1/j1 - 16-bit bpv (bipolar pulse viol ation)/excess zero/prbs or qrss error counter - analog loopback, digital loopback, remote loopback and inband loopback ? per channel cable attenuation indication ? adaptive receive sensitivity ? non-intrusive monitoring per itu g.772 specification ? short circuit protection for line drivers ? los (loss of signal) & ais (ala rm indication signal) detection ? jtag interface ? supports serial control interface, motorola and intel non-multi- plexed interfaces ? package: idt82v2084: 128-pin tqfp description: the idt82v2084 can be configured as a quad t1, quad e1 or quad j1 line interface unit. in receive path, an adaptive equalizer is integrated to remove the distortion introduced by t he cable attenuation. the idt82v2084 also performs clock/data recovery, ami/b8zs/hdb3 line decoding and detects and reports the los conditions . in transmit path, there is an ami/ b8zs/hdb3 encoder, waveform shaper and lbos. there is one jitter attenuator for each channel, which can be placed in either the receive path or the transmit path. the jitter att enuator can also be disabled. the idt82v2084 supports both single rail and dual rail system interfaces and both serial and parallel control interfaces. to facilitate the network mainte- nance, a prbs/qrss generation/detecti on circuit is integrated in each channel, and different types of loopbac ks can be set on a per channel basis. four different kinds of line terminating impedance, 75 ? , 100 ?, 110 ? and 120 ? are selectable on a per channel basis. the chip also provides driver short-circuit protection and supports jtag boundary scanning. the idt82v2084 can be used in sdh/sonet, lan, wan, routers, wireless base stations, iads, im as, imaps, gateways, frame relay access devices, csu/dsu equipment, etc. industrial temperature ranges july 2004 the idt logo is a registered trademark of integrated device technology, inc.
2 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit functional block diagram figure-1 block diagram analog loopback one of the four identical channels microprocessor interface clock generator cs sclk ds / rd sdi/r/ w / wr sdo int d[7:0] a[7:0] mclk trst tck tms tdi tdo jtag tap b8zs/ hdb3/ami encoder jitter attenuator line driver waveform shaper/lbo b8zs/ hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detector clock and data recovery vddd vddio vdda vddt digital loopback remote loopback g.772 monitor transmitter internal termination receiver internal termination tclkn tdnn tdn/tdpn rclkn cvn/rdnn losn rdn/rdpn rringn ttipn tringn rtipn prbs detector iblc detector prbs generator iblc generator taos mclks vddr basic control p/ s int/ mot thz ref rst sclke
3 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table of contents 1 idt82v2084 pin configurations ................. ................ ................. .............. .............. ............ 8 2 pin description ...... ................ ................. ................ .............. .............. .............. ............. ......... 9 3 functional description ............... ................ ................ ............... .............. .............. .......... 14 3.1 t1/e1/j1 mode selection ................ ................. ................ ................. .............. .......... 14 3.2 transmit path ............ ................ ................. ................ ................. ................ ............... 1 4 3.2.1 transmit path system interf ace.............. .............. .............. ............ ........ 14 3.2.2 encoder ........... ................ ................ .............. ............... .............. .............. .......... 14 3.2.3 pulse shaper ............ ................. ................ ................. .............. .............. .......... 14 3.2.3.1 preset pulse templates .... ................ ................. .............. .............. ......... 14 3.2.3.2 lbo (line build out) ...... ................. ................ ................. .............. ......... 15 3.2.3.3 user-programmable arbitrary waveform .. ............. .............. ............ ....... 15 3.2.4 transmit path line interfac e................ ............... .............. .............. .......... 19 3.2.5 transmit path power down .. ................. ............... .............. .............. .......... 19 3.3 receive path .............. ................ ................. ................ ................. ................ ............... 20 3.3.1 receive internal terminatio n.................. .............. .............. .............. ........ 20 3.3.2 line monitor ............ ................ ................. ................ ................. .............. .......... 21 3.3.3 adaptive equalizer.... ................ ................ ............... .............. .............. .......... 21 3.3.4 receive sensitivity ............. ................ ................. ................ ................. .......... 21 3.3.5 data slicer .............. ................ ................. ................ ................. .............. .......... 21 3.3.6 cdr (clock & data recovery)... ............... ................ ................. ................ ............. 21 3.3.7 decoder ........... ................ ................ .............. ............... .............. .............. .......... 21 3.3.8 receive path system interface ................ .............. .............. ............ ........ 21 3.3.9 receive path power down.... ................ ................. .............. .............. .......... 21 3.3.10 g.772 non-intrus ive monitoring ........... ............... .............. .............. .......... 22 3.4 jitter attenuator ........ ................ ................ ................. ................ ................. .......... 23 3.4.1 jitter attenuation functi on description ............... ................ ............. 23 3.4.2 jitter attenuator performa nce ............... ................. ................ ............. 23 3.5 los and ais detection ............ .............. .............. ............... .............. .............. .......... 24 3.5.1 los detection ......... ................ ................. ................ ................. .............. .......... 24 3.5.2 ais detection .......... ................ ................. ................ ................. .............. .......... 25 3.6 transmit and detect internal patterns ...... .............. .............. .............. ........ 26 3.6.1 transmit all ones ... ................. ................ ................. .............. .............. .......... 26 3.6.2 transmit all zeros.... ................ ................ ............... .............. .............. .......... 26 3.6.3 prbs/qrss generation and detection..... ............. .............. ............ ........ 26 3.7 loopback ............ ................ ................ .............. .............. ............... .............. .............. ... 26 3.7.1 analog loopback ....... ................ ................ ............... .............. .............. .......... 26 3.7.2 digital loopback ..... ................. ................ ................. .............. .............. .......... 26 3.7.3 remote loopback....... ................ ................ ............... .............. .............. .......... 26 3.7.4 inband loopback...... ................. ................ ................. .............. .............. .......... 28 3.7.4.1 transmit activate/deacti vate loopback code.... .............. .............. ......... 28 3.7.4.2 receive activate/deact ivate loopback code..... .............. .............. ......... 28 3.7.4.3 automatic remote loopback .............. ............... .............. .............. ......... 28 table of contents
4 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.8 error detection/counting and insertion ........... ................ ................. .......... 29 3.8.1 definition of line coding error .......... ............... .............. .............. .......... 29 3.8.2 error detection and counti ng ................ .............. .............. ............ ........ 29 3.8.3 bipolar violation and prbs error insertion ......... ................ ............. 30 3.9 line driver failure monitoring ............... ................. ................ ................. .......... 30 3.10 mclk and tclk ..... ................ ................. ................ .............. .............. .............. ............. 31 3.10.1 master clock (mclk) .......... ................ ................. ................ ................. .......... 31 3.10.2 transmit clock (tclk)........ ................ ................. ................ ................. .......... 31 3.11 microcontroller interfaces .. ............... ................. ................ ................. .......... 32 3.11.1 parallel microcontroller interface............. .............. .............. .......... 32 3.11.2 serial microcontroller interface .......... ................. ................ ............. 32 3.12 interrupt handling ... ................. ................ ................ ................. ................ ............. 33 3.13 5v tolerant i/o pins ............. ................ ................ ............... .............. .............. .......... 33 3.14 reset operation ......... ................. ................ ................ ................. ................ ............. 33 3.15 power supply ............ ................ ................. ................ ................. ................ ............... 3 3 4 programming information ............. .............. .............. ............... .............. .............. .......... 34 4.1 register list and map .. ............... ................ ................. ................ ................. .......... 34 4.2 register description .... ................ ................. ................ ................. .............. .......... 36 4.2.1 global registers.... ................. ................ ................. .............. .............. .......... 36 4.2.2 jitter attenuation control register ..... ................. ................ ............. 37 4.2.3 transmit path control regi sters................ ................ ................. .......... 38 4.2.4 receive path control regi sters ............. .............. .............. ............ ........ 40 4.2.5 network diagnost ics control registers ................ ................. .......... 42 4.2.6 interrupt control registers .............. ............... .............. .............. .......... 45 4.2.7 line status registers ....... ................ ................. ................ ................. .......... 48 4.2.8 interrupt status registers . ................ ............... .............. .............. .......... 51 4.2.9 counter registers ... ................ ................ ............... .............. .............. .......... 52 4.2.10 transmit and receive te rmination register .......... ................ ............. 53 5 ieee std 1149.1 jtag test access po rt ............... ................ ................. .............. .......... 54 5.1 jtag instructions and instru ction register .... ................ ................. .......... 55 5.2 jtag data register .... ................. ................ ................ ................. ................ ............. 55 5.2.1 device identification regi ster (idr) ............. ................ ................. .......... 55 5.2.2 bypass register (br) ................. ................ ............... .............. .............. .......... 55 5.2.3 boundary scan regi ster (bsr) ............. ............... .............. .............. .......... 55 5.2.4 test access port controller . ................. .............. .............. ............ ........ 56 6 test specifications ......... ................ ................ ................. ................ ................. ............... .. 58 7 microcontroller interface timi ng characteristics ............ ................ ............. 70 7.1 serial interface timing ......... .............. .............. ............... .............. .............. .......... 70 7.2 parallel interface timing ....... ................ ................ ................. ................ ............. 71
5 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit list of tables table-1 pin description ....... ................ ................. ................ ................. ................ ................ ....... 9 table-2 transmit wavefo rm value for e1 75 ? ................ ................ ................. .............. ......... 16 table-3 transmit wavefo rm value for e1 120 ? ................ ................. .............. .............. ......... 16 table-4 transmit waveform value for t1 0~133 ft........... ................ ................. .............. ......... 16 table-5 transmit waveform value for t1 133~266 ft.............. .............. .............. .............. ....... 16 table-6 transmit waveform value for t1 266~399 ft.............. .............. .............. .............. ....... 17 table-7 transmit waveform value for t1 399~533 ft.............. .............. .............. .............. ....... 17 table-8 transmit waveform value for t1 533~655 ft.............. .............. .............. .............. ....... 17 table-9 transmit waveform value for j1 0~655 ft .................. .............. .............. .............. ....... 17 table-10 transmit waveform value for ds 1 0 db lbo............... .............. .............. ............ ....... 18 table-11 transmit waveform value for ds 1 -7.5 db lbo .......... .............. .............. ............ ....... 18 table-12 transmit waveform value for ds1 -15.0 db lbo ........ .............. .............. ............ ....... 18 table-13 transmit waveform value for ds1 -22.5 db lbo ........ .............. .............. ............ ....... 18 table-14 impedance matching for transmit ter ............... ................ ................. ................ ............ 19 table-15 impedance matching for receiver .............. .............. ............... .............. .............. ......... 20 table-16 criteria of starting speed adjustment....... ................ ............... .............. .............. ......... 23 table-17 los declare and clear criteria for short haul mode .. .............. .............. .............. ....... 24 table-18 los declare and clear criteria for long haul mode..... .............. .............. ............ ....... 25 table-19 ais condition ......... ................ ................. ................ ................. ................ ............... ...... 25 table-20 criteria for setting/clearing the prbs_s bit ..... ................. ................ ................. ......... 26 table-21 exz definition ........ ................ ................. ................ ................. ................ ............... ...... 29 table-22 interrupt event................. ................. .............. .............. .............. .............. .............. ....... 33 table-23 global register list and map............... ................. ................ ................. .............. ......... 34 table-24 per channel register list and map ............ .............. ............... .............. .............. ......... 35 table-25 id: chip revision regi ster ................... ................. ................ .............. .............. ............ 36 table-26 rst: reset register ... ................ ................ ................. ................ ................. ............... . 36 table-27 gcf0: global configur ation register 0 ........... ................ ................. ................ ............ 36 table-28 gcf1: global configur ation register 1 ........... ................ ................. ................ ............ 37 table-29 intch: interrupt channel indi cation register........... ............... .............. .............. ......... 37 table-30 jacf: jitter attenua tor configuration register .. ................. ................ ................. ......... 37 table-31 tcf0: transmitter configuratio n register 0 ............. ............... .............. .............. ......... 38 table-32 tcf1: transmitter configuratio n register 1 ............. ............... .............. .............. ......... 38 table-33 tcf2: transmitter configuratio n register 2 ............. ............... .............. .............. ......... 39 table-34 tcf3: transmitter configuratio n register 3 ............. ............... .............. .............. ......... 39 table-35 tcf4: transmitter configuratio n register 4 ............. ............... .............. .............. ......... 39 table-36 rcf0: receiver configuration register 0................. ............... .............. .............. ......... 40 table-37 rcf1: receiver configuration register 1................. ............... .............. .............. ......... 41 table-38 rcf2: receiver configuration register 2................. ............... .............. .............. ......... 42 table-39 maint0: maintenance function control register 0..... .............. .............. .............. ....... 42 table-40 maint1: maintenance function control register 1..... .............. .............. .............. ....... 43
6 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-41 maint2: maintenance function control register 2..... .............. .............. .............. ....... 43 table-42 maint3: maintenance function control register 3..... .............. .............. .............. ....... 43 table-43 maint4: maintenance function control register 4..... .............. .............. .............. ....... 44 table-44 maint5: maintenance function control register 5..... .............. .............. .............. ....... 44 table-45 maint6: maintenance function control register 6..... .............. .............. .............. ....... 44 table-46 intm0: interrupt mask register 0 ............... .............. ............... .............. .............. ......... 45 table-47 intm1: interrupt mask register 1 ............... .............. ............... .............. .............. ......... 46 table-48 intes: interrupt tr igger edges select register ................. ................ ................. ......... 47 table-49 stat0: line status register 0 (real time status m onitor)............ .............. ............ ....... 48 table-50 stat1: line status register 1 (real time status m onitor)............ .............. ............ ....... 50 table-51 ints0: interrupt stat us register 0 ....... ................. ................ ................. .............. ......... 51 table-52 ints1: interrupt stat us register 1 ....... ................. ................ ................. .............. ......... 52 table-53 cnt0: error count er l-byte register 0....... .............. ............... .............. .............. ......... 52 table-54 cnt1: error counter h- byte register 1 ........... ................ ................. ................ ............ 52 table-55 term: transmit and receive termination configuration regist er ................ .............. 53 table-56 instruction regi ster description ......... ................ ................. ................ ................. ......... 55 table-57 device identification register description........ ................ ................. ................ ............ 55 table-58 tap controller state descripti on ................ .............. ............... .............. .............. ......... 56 table-59 absolute maximum rating ........ ................ ................ ............... .............. .............. ......... 58 table-60 recommended operation conditions ................ ................. ................ ................. ......... 58 table-61 power consumption.... ................ ................ ................. ................ ................. ................ 59 table-62 dc characteristics ............... ................ .............. .............. ............... .............. ............. ... 59 table-63 e1 receiver electric al characteristics ............. ................ ................. ................ ............ 60 table-64 t1/j1 receiver electrical char acteristics................ ................. .............. .............. ......... 61 table-65 e1 transmitter electr ical characteristics ......... ................ ................. ................ ............ 62 table-66 t1/j1 transmitter electrical characteristics..... ................ ................. ................ ............ 63 table-67 transmitter and receiver timing char acteristics ............ ................. ................ ............ 64 table-68 jitter tolerance ...... ................ ................. ................ ................. ................ ............... ...... 65 table-69 jitter attenuator char acteristics ........... ................. ................ ................. .............. ......... 6 7 table-70 jtag timing char acteristics ............... ................. ................ ................. .............. ......... 69 table-71 serial interface timing charac teristics ....... .............. ............... .............. .............. ......... 70 table-72 non_multiplexed motorola read timing characteristics ........... .............. .............. ....... 71 table-73 non_multiplexed motorola wr ite timing characteristics ........... .............. .............. ....... 72 table-74 non_multiplexed intel read ti ming characteristics ...... .............. .............. ............ ....... 73 table-75 non_multiplexed intel write timing characteristics................. .............. .............. ......... 74
7 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit list of figures figure-1 block diagram ....... ................ ................. ................ ................. ................ ................ ........ 2 figure-2 idt82v2084 tqfp128 pa ckage pin assignment ... ............... .............. .............. ............ 8 figure-3 e1 waveform template diagram ............... .............. ............... .............. .............. .......... 14 figure-4 e1 pulse template test circuit .............. ................ ................. .............. .............. .......... 14 figure-5 dsx-1 waveform template ..... ................ ................ ............... .............. .............. .......... 14 figure-6 t1 pulse template te st circuit ........... ................. ................ ................. .............. .......... 15 figure-7 receive path function block dia gram .............. ................. ................ ................. .......... 20 figure-8 transmit/receive line circuit .. ................ ................ ............... .............. .............. .......... 20 figure-9 monitoring receive line in anot her chip ................. ............... .............. .............. .......... 21 figure-10 monitor transmit line in another chip ... ................ ................. .............. .............. .......... 21 figure-11 g.772 monitoring diagram ....... ................ .............. .............. .............. .............. ............. 2 2 figure-12 jitter attenuator ... ................ ................ ................. ................ ................. ............... ......... 23 figure-13 los declare and clear ......... ................. .............. .............. .............. .............. .............. .24 figure-14 analog loopback ......... ................ ................. ................ ................. .............. ............. .... 27 figure-15 digital loopback .... ................ ................. ................ ................. ................ ............... ....... 27 figure-16 remote loopback ...... ................ ................ ................. ................ ................. .............. ... 27 figure-17 auto report mode ............... ................ .............. .............. ............... .............. ............. .... 29 figure-18 manual report mode ................ .............. .............. .............. .............. .............. ............. .. 30 figure-19 tclk operation flowchart .... ................. ................ .............. .............. .............. ............. 3 1 figure-20 serial processor interface f unction timing ............. ............... .............. .............. .......... 32 figure-21 jtag architecture .. ............... .............. .............. .............. ............... .............. ............ ..... 54 figure-22 jtag state diagram .. ................ ................ ................. ................ ................. ............... .. 57 figure-23 transmit system interface ti ming .................. ................ ................. ................ ............. 65 figure-24 receive system interface timi ng .............. .............. ............... .............. .............. .......... 65 figure-25 e1 jitter tolerance performanc e ............... .............. ............... .............. .............. .......... 66 figure-26 t1/j1 jitter tolera nce performance ....... ................ ................. .............. .............. .......... 66 figure-27 e1 jitter transfer performance ........... ................. ................ ................. .............. .......... 68 figure-28 t1/j1 jitter transfe r performance ......... ................ ................. .............. .............. .......... 68 figure-29 jtag interface timing ........ ................ ................. .............. .............. .............. ............. .. 69 figure-30 serial interface write timing ............... ................. .............. .............. .............. .............. .70 figure-31 serial interface read timing with sclke=1 ........... ............... .............. .............. .......... 70 figure-32 serial interface read timing with sclke=0 ........... ............... .............. .............. .......... 70 figure-33 non_multiplexed motorola r ead timing ........... ................. ................ ................. .......... 71 figure-34 non_multiplexed motorola writ e timing ........... ................. ................ ................. .......... 72 figure-35 non_multiplexed intel read timi ng .................. ................. ................ ................. .......... 73 figure-36 non_multiplexed intel write ti ming .................. ................. ................ ................. .......... 74
8 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 1 idt82v2084 pin configurations figure-2 idt82v2084 tqfp 128 package pin assignment idt82v2084 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 los2 los3 los4 thz sclke int/ mot ic p/ s vddd mclk gndd gndio vddio d7 d6 d5 d4 d3 d2 d1 d0 vddio gndio a7 a6 a5 a4 a3 a2 a1 a0 cs sclk ds / rd sdi/r/ w / wr sdo int rst vddr4 rtip4 rring4 gndr4 gndt4 gndt4 ttip4 tring4 vddt4 vddt4 vddr3 rtip3 rring3 gndr3 gndt3 gndt3 ttip3 tring3 vddt3 vddt3 vdda ref ic gnda mclks ic vddt1 vddt1 nc vddio gndio tclk1 td1/tdp1 tdn1 rclk1 rd1/rdp1 cv1/rdn1 tclk2 td2/tdp2 tdn2 rclk2 rd2/rdp2 cv2/rdn2 vddd gndd gndio tclk3 vddio td3/tdp3 tdn3 rclk3 rd3/rdp3 cv3/rdn3 tclk4 td4/tdp4 tdn4 rclk4 rd4/rdp4 cv4/rdn4 gndio vddio nc nc nc tring1 ttip1 gndt1 gndt1 gndr1 rring1 rtip1 vddr1 vddt2 vddt2 tring2 ttip2 gndt2 gndt2 gndr2 rring2 rtip2 vddr2 vdda gnda trst tms tdi tdo tck los1
9 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 2 pin description table-1 pin description name type tqfp128 description transmit and receive line interface ttip1 ttip2 ttip3 ttip4 tring1 tring2 tring3 tring4 output analog 104 114 48 58 103 113 47 57 ttipn 1 /tringn: transmit bipolar tip/ring for channel 1~4 these pins are the differential line driver outputs and can be set to high impedance state globally or individually. a logic hi gh on thz pin turns all these pins into high impedance state. when thz bit ( tcf1, 03h... ) 2 is set to ?1?, the ttipn/tringn in the cor- responding channel is set to high impedance state. in summary, these pins will become high impedance in the following conditions: ? thz pin is high: all ttipn/tringn enter high impedance. ? thzn bit is set to 1: the corresponding ttipn/tringn become high impedance; ? loss of mclk: all ttipn/tringn pins become high impedance; ? loss of tclkn: the corresponding ttipn/tringn become high impedance (exceptions: remote loopback; transmit internal pattern by mclk); ? transmitter path power down: the corresponding ttipn/tringn become high impedance; ? after software reset; pin reset and power on: all ttipn/tringn enter high impedance. rtip1 rtip2 rtip3 rtip4 rring1 rring2 rring3 rring4 input analog 109 119 53 63 108 118 52 62 rtipn/rringn: receive bipolar tip/ring for channel 1~4 these pins are the differential line receiver inputs. transmit and receive digital data interface td1/tdp1 td2/tdp2 td3/tdp3 td4/tdp4 tdn1 tdn2 tdn3 tdn4 input 96 90 80 74 95 89 79 73 tdn: transmit data for channel 1~4 in single rail mode, the nrz data to be transmitted is input on these pins. data on tdn is sampled into the device on the activ e edge of tclkn. the active edge of tclkn is selected by the tclk_sel bit ( tcf0, 02h... ). data is encoded by ami, hdb3 or b8zs line code rules before being transmitted to the line. in this mode, tdnn should be connected to ground. tdpn/tdnn: positive/negative transmit data for channel 1~4 in dual rail mode, the nrz data to be transmitted is input on these pins. data on tdpn/tdnn is sampled into the device on the active edge of tclkn. the active edge of the tclkn is selected by the tclk_sel bit ( tcf0, 02h... ) the line code in dual rail mode is as follows: tclk1 tclk2 tclk3 tclk4 input 97 91 82 75 tclkn: transmit clock for channel 1~4 these pins input 1.544 mhz for t1/j1 mode or 2.048 mhz for e1 mode transmit clock. the tran smit data on tdn/tdpn or tdnn is sampled into the device on the active edge of tclkn. if tclkn is missing 3 and the tclkn missing interrupt is not masked, an interrupt will be generated. tdpn tdnn output pulse 00space 0 1 positive pulse 1 0 negative pulse 11space notes: 1. the footprint ?n? (n = 1~4) r epresents one of the four channels. 2. the name and address of the registers that contain the precedin g bit. only the address of channel 1 register is listed, the r est addresses are represented by '...'. users can find these omitted addresses in the register description section. 3. tclkn missing: the state of tclkn continues to be high level or low level over 70 clock cycles.
10 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit rd1/rdp1 rd2/rdp2 rd3/rdp3 rd4/rdp4 cv1/rdn1 cv2/rdn2 cv3/rdn3 cv4/rdn4 output 93 87 77 71 92 86 76 70 rdn: receive data for channel 1~4 in single rail mode, the nrz receive data is output on these pins. data is decoded according to ami, hdb3 or b8zs line code rules. the active level on rdn pin is selected by the rd_inv bit ( rcf0, 07h... ). cvn: code violation for channel 1~4 in single rail mode, the bpv/cv errors in received data streams will be reported by driving pin cvn to high level for a full cl ock cycle. the b8zs/hdb3 line code violation can be indicated when the b8zs/hdb3 decoder is enabled. when ami decoder is selected, the bipolar violation can be indicated. rdpn/rdnn: positive/negative receive data for channel 1~4 in dual rail mode with clock & data recovery (cdr), these pins output the nrz data with the recovered clock. an active level on rdpn indicates the receipt of a positive pulse on rtipn/rringn while an active level on rdnn indicates the receipt of a neg- ative pulse on rtipn/rringn. the active level on rdpn/rdnn is selected by the rd_inv bit (rcf0, 07h...). when cdr is disabled, these pins directly output the raw rz sliced data. the output data on rdn and rdpn/rdnn is updated on the active edge of rclkn. rclk1 rclk2 rclk3 rclk4 output 94 88 78 72 rclkn: receive clock for channel 1~4 these pins output 1.544 mhz for t1/j1 mode or 2.048 mhz for e1 mode receive clock. under los conditions, if aise bit ( maint0, 0ah... ) is ?1?, rclkn is derived from mclk. in clock recovery mode, these pins provide the clock recovered from the signal received on rtipn/rringn. the receive data (rdn in single rail mode or rdpn/rdnn in dual rail mode) is updated on the active edge of rclkn. the active edge is selected by the rclk_sel bit ( rcf0, 07h... ). if clock recovery is bypassed, rclkn is the exclusive or(xor) ou tput of the dual rail sliced data rdpn and rdnn. this signal can be used in the applications with external clock recovery circuitry. mclk input 10 mclk: master clock mclk is an independent, free-running reference clock. it is a single reference for all operation modes and provides selectable 1.544 mhz or 37.056 mhz for t1/j1 operating mode, while 2.048 mhz or 49.152 mhz for e1 operating mode. the reference clock is used to generate several internal reference signals: ? timing reference for the integrated clock recovery unit. ? timing reference for the integrated digital jitter attenuator. ? timing reference for mi crocontroller interface. ? generation of rclkn signal during a loss of signal condition. ? reference clock during transmit all ones (tao) and all zeros condition. when sending prbs/qrss or inband loopback code, either mclk or tclkn can be selected as the reference clock. ? reference clock for atao and ais. the loss of mclk will turn all the four ttip/tring into high impedance status. mclks input 40 mclks: master clock select if 2.048 mhz (e1) or 1.544 mhz (t1/j1) is se lected as the mclk, this pin should be connected to ground; and if the 49.152 mhz (e1) or 37.056 mhz (t1/j1) is selected as the mclk, this pin should be pulled high. los1 los2 los3 los4 output 128 1 2 3 losn: loss of signal output for channel 1~4 these pins are used to indicate the loss of received signals. when losn pin becomes high, it indicates the loss of received sig - nals in channel n. the losn pin will become low automatically when valid received signal is detected again. the criteria of los s of signal are described in 3.5 los and ais detection . control interface p/ s input 8 p/ s : parallel or serial control interface select level on this pin determines which control mode is selected to control the device as follows: the serial microcontroller interface consists of cs , sclk, sdi, sdo and sclke pins. parallel microcontroller interface consists of cs , a[7:0], d[7:0], ds / rd and r/ w / wr pins. the device supports non-multiplexed parallel interface as follows: table-1 pin description (continued) name type tqfp128 description p/ s control interface high parallel microcontroller interface low serial microcontroller interface p/ s , int/ mot microcontroller interface 10 motorola non-multiplexed 11 intel non-multiplexed
11 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit int/ mot input 6 int/ mot : intel or motorola microcontroller interface select in microcontroller mode, the parallel microcontroller interface is configured for motorola compatible microcontrollers when thi s pin is low, or for intel compatible microcontrollers when this pin is high. cs input 32 cs : chip select in microcontroller mode, this pin is asserted low by the microcontroller to enable microcontroller interface. for each read or write operation, this pin must be changed from high to low, and will remain low until the operation is over. sclk input 33 sclk: shift clock in serial microcontroller mode, signal on this pin is the shift clock for the serial interface. configuration data on pin sdi i s sampled on the rising edges of sclk. configuration and status data on pin sdo is clocked out of the device on the rising edges of sclk if pin sclke is low, or on the falling edges of sclk if pin sclke is high. ds / rd input 34 ds : data strobe in parallel motorola microcontroller interface mode, signal on this pin is the data strobe of the parallel interface. during a write operation (r/ w =0), data on d[7:0] is sampled into the device. during a read operation (r/ w =1), data is output to d[7:0] from the device. rd : read operation in parallel intel microcontroller interface mode, this pin is asserted low by the microcontroller to initiate a read cycle. dat a is out- put to d[7:0] from the device during a read operation. sdi/r/ w / wr input 35 sdi: serial data input in serial microcontroller mode, data is input on this pin. input data is sampled on the rising edges of sclk. r/ w : read/write select in parallel motorola microcontroller interface mode, this pin is low for write operation and high for read operation. wr : write operation in parallel intel microcontroller interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. da ta on d[7:0] is sampled into the device during a write operation. sdo output 36 sdo: serial data output in serial microcontroller mode, signal on this pin is the output data of the serial interface. configuration and status data on pin sdo is clocked out of the device on the active edge of sclk. int output 37 int : interrupt request this pin outputs the general interrupt request for all interrupt sources. if intm_glb bit ( gcf0, 40h ) is set to ?1? all the interrupt sources will be masked. and these interrupt sources also can be masked individually via registers ( intm0, 11h ) and ( intm1, 12h ). interrupt status is reported via byte int_ch ( intch, 80h ), registers ( ints0, 16h ) and ( ints1, 17h ). output characteristics of this pin can be defined to be push-pul l (active high or low) or be open-drain (active low) by bits int_pin[1:0] ( gcf0, 40h ). d7 d6 d5 d4 d3 d2 d1 d0 i / o tri-state 14 15 16 17 18 19 20 21 dn: data bus 7~0 these pins function as a bi-directional data bus of the microcontroller interface. a7 a6 a5 a4 a3 a2 a1 a0 input 24 25 26 27 28 29 30 31 an: address bus 7~0 these pins function as an address bus of the microcontroller interface. rst input 38 rst : hardware reset the chip is reset if a low signal is applied on this pin for more than 100ns. all the drivers output are in high-impedance stat e, all the internal flip-flops are reset and all the registers are initialized to their default values. table-1 pin description (continued) name type tqfp128 description
12 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit thz input 4 thz: transmit driver enable this pin enables or disables all transmitter drivers on a global basis. a low level on this pin enables the drivers while a hig h level turns all drivers into high impedance state. note that functionality of internal circuits is not affected by signal on this pin . ref input 43 ref: re ference resistor an external resistor (3 k ?, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit. sclke input 5 sclke: serial clock edge select signal on this pin determines the active edge of sclk to output sdo. the active clock edge is selected as shown below: jtag signals trst input pullup 123 trst : jtag test port reset this is the active low asynchronous reset to the jtag test port. this pin has an internal pull-up resistor. to ensure determini stic operation of the test logic, tms should be held high while the signal applied to trst changes from low to high. for normal signal processing, this pin should be connected to ground. tms input pullup 124 tms: jtag test mode select this pin is used to control the test logic state machine and is sampled on the rising edges of tck. tms has an internal pull-up resistor. tck input 127 tck: jtag test clock this pin is the input clock for jtag. the data on tdi and tms is clocked into the device on the rising edges of tck while the data on tdo is clocked out of the device on the falling edges of tck. when tck is idle at a low level, all stored-state devices contained in the test logic will retain their state indefinitely. tdo output tri-state 126 tdo: jtag test data output this is a tri-state output signal and used for reading all the serial configuration and test data from the test logic. the data on tdo is clocked out of the device on the falling edges of tck. tdi input pullup 125 tdi: jtag test data input this pin is used for loading instructions and data into the test logic and has an internal pullup resistor. the data on tdi is clocked into the device on the rising edges of tck. power supplies and grounds vddio - 13, 22 68, 81 99 3.3v i/o power supply gndio - 12, 23 69, 83 98 i/o ground vddt1 vddt2 vddt3 vddt4 - 101, 102 111, 112 45, 46 55, 56 3.3v power supply for transmitter driver gndt1 gndt2 gndt3 gndt4 - 105, 106 115, 116 49, 50 59, 60 analog ground for transmitter driver vdda - 44, 121 3.3v analog core power supply gnda - 41, 122 core analog ground vddd - 9, 85 3.3v digital core power supply gndd - 11, 84 core digital ground vddr1 vddr2 vddr3 vddr4 - 110 120 54 64 3.3v power supply for receiver table-1 pin description (continued) name type tqfp128 description sclke sclk low rising edge is active edge high falling edge is active edge
13 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit gndr1 gndr2 gndr3 gndr4 - 107 117 51 61 analog ground for receiver others ic - 39 7 ic: internal connection internal use. these pins should be connected to ground when in normal operation. ic - 42 ic: internal connection internal use. this pin should be left open when in normal operation. nc - 65, 66 67, 100 nc: no connection table-1 pin description (continued) name type tqfp128 description
14 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3 functional description 3.1 t1/e1/j1 mode selection the idt82v2084 can be used as a fou r-channel e1 liu or a four-chan- nel t1/j1 liu. in e1 application, the t1e1 bit ( gcf0, 40h ) should be set to ?0?. in t1/j1 application, the t1e1 bit should be set to ?1?. 3.2 transmit path the transmit path of each channel of the idt82v2084 consists of an encoder, an optional jitter attenuator, a waveform shaper, a set of lbos, a line driver and a programm able transmit termination. 3.2.1 transmit path system interface the transmit path system interface consists of tclkn pin, tdn/tdpn pin and tdnn pin. in e1 mode, the tc lkn is a 2.048 mhz clock. in t1/j1 mode, the tclkn is a 1.544 mhz clock. if the tclkn is missing for more than 70 mclk cycles, an interrupt wi ll be generated if it is not masked. transmit data is sampled on the tdn/ tdpn and tdnn pins by the active edge of tclkn. the active edge of tclkn can be selected by the tclk_sel bit ( tcf0, 02h... ). and the active level of the data on tdn/tdpn and tdnn can be selected by the td_inv bit ( tcf0, 02h... ). the transmit data from the system si de can be provided in two different ways: single rail and dual rail. in si ngle rail mode, only tdn pin is used for transmitting data and the t_md[1] bit ( tcf0, 02h... ) should be set to ?0?. in dual rail mode, both tdpn and tdnn pins are used for transmitting data, the t_md[1] bit ( tcf0, 02h... ) should be set to ?1?. 3.2.2 encoder when t1/j1 mode is selected, in si ngle rail mode, the encoder can be selected to be a b8zs encoder or an ami encoder by setting t_md[0] bit ( tcf0, 02h... ). when e1 mode is selected, in single rail mode, the encoder can be con- figured to be a hdb3 encoder or an ami encoder by setting t_md[0] bit ( tcf0, 02h... ). in both t1/j1 mode and e1 mode, when dual rail mode is selected (bit t_md[1] is ?1?), the encoder is by-pass ed. in the dual rail mode, a logic ?1? on the tdpn pin and a logic ?0? on the tdnn pin results in a negative pulse on the ttipn/tringn; a logic ?0? on td pn pin and a logic ?1? on tdnn pin results in a positive pulse on the ttipn/tringn. if both tdpn and tdnn are logic ?1? or logic ?0?, the ttip n/tringn outputs a space (refer to tdn/ tdpn, tdnn pin description ). 3.2.3 pulse shaper the idt82v2084 provides three ways of manipulating the pulse shape before sending it. the first is to us e preset pulse templates for short haul application, the second is to use lbo (line build out) for long haul appli- cation and the other way is to use us er-programmable arbitrary waveform template. 3.2.3.1 preset pulse templates for e1 applications, the pulse shape is shown in figure-3 according to the g.703 and the measuring diagram is shown in figure-4 . in internal impedance matching mode, if the cable impedance is 75 ? , the puls[3:0] bits ( tcf1, 03h... ) should be set to ?0000?; if the cable impedance is 120 ? , the puls[3:0] bits ( tcf1, 03h... ) should be set to ?0001?. in external impedance matching mode, for both e1/75 ? and e1/120 ? cable imped- ance, puls[3:0] should be set to ?0001?. figure-3 e1 waveform template diagram figure-4 e1 pulse template test circuit for t1 applications, the pulse shape is shown in figure-5 according to the t1.102 and the measuring diagram is shown in figure-6. this also meets the requirement of g.703, 2001. the cable length is divided into five grades, and there are five pulse templates used for each of the cable length. the pulse template is selected by puls[3:0] bits ( tcf1, 03h... ). figure-5 dsx-1 waveform template -0.6 -0.4 -0.2 0 0.2 0.4 0.6 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 tim e in u nit intervals normalized amplitude idt82v2084 v out r load ttipn tringn note: 1. for r load = 75 ? (nom), v out (peak)=2.37v (nom) 2. for r load =120 ? (nom), v out (peak)=3.00v (nom) -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 0 250 500 750 1000 1250 time (ns) normalized amplitude
15 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit figure-6 t1 pulse template test circuit for j1 applications, the puls[3:0] ( tcf1, 03h.. .) should be set to ?0111?. table-14 lists these values. 3.2.3.2 lbo (line build out) to prevent the cross-talk at the fa r end, the output of ttip/tring could be attenuated before transmission for l ong haul applications. the fcc part 68 regulations specifies four grades of attenuation with a step of 7.5 db. three lbos are used to implement the pulse attenuation. the puls[3:0] bits ( tcf1, 03h... ) are used to select the attenuation grade. both table-14 and table-15 list these values. 3.2.3.3 user-programmable arbitrary waveform when the puls[3:0] bits are set to ?11xx?, user-progr ammable arbitrary waveform generator mode can be used in the corresponding channel. this allows the transmitter performance to be tuned for a wide variety of line con- dition or special application. each pulse shape can extend up to 4 uis (unit interval), addressed by ui[1:0] bits ( tcf3, 05h... ) and each ui is divided into 16 sub-phases, addressed by the samp[3:0] bits ( tcf3, 05h... ). the pulse amplitude of each phase is represented by a binary by te, within the range from +63 to - 63, stored in wdat[6:0] bits ( tcf4, 06h... ) in signed magnitude form. the most positive number +63 (d) repres ents the maximum positive amplitude of the transmit pulse while the most negative number -63 (d) represents the maximum negative amplitude of the transmit pulse. therefore, up to 64 bytes are used. for each channel, a 64 bytes ram is available. there are twelve standard templates which are stored in a local rom. user can select one of them as reference and make some changes to get the desired waveform. user can change the wave shape and the amplitude to get the desired pulse shape. in order to do this, firstl y, users can choose a set of waveform value from the following twelve tables , which is the most similar to the desired pulse shape. table-2 , table-3 , table-4 , table-5 , table-6 , table-7 , table-8 , table-9 , table-10 , table-11 , table-12 and table-13 list the sample data and scaling data of each of the twelve templates. then modify the cor- responding sample data to get the desired transmit pulse shape. secondly, through the value of sc al[5:0] bits increased or decreased by 1, the pulse amplitude can be scale d up or down at the percentage ratio against the standard pulse amplitude if needed. for different pulse shapes, the value of scal[5:0] bits and the scaling percentage ratio are different. the following twelve tables list these values. do the followings step by step, the desired waveform can be pro- grammed, based on the selected waveform template: (1).select the ui by ui[1:0] bits ( tcf3, 05h... ) (2).specify the sample address in the selected ui by samp [3:0] bits ( tcf3, 05h... ) (3).write sample data to wdat[6:0] bits ( tcf4, 06h... ). it contains the data to be stored in the ram, addressed by the selected ui and the corresponding sample address. (4).set the rw bit ( tcf3, 05h... ) to ?0? to implement writing data to ram, or to ?1? to implement read data from ram (5).implement the read from ram/write to ram by setting the done bit ( tcf3, 05h... ) repeat the above steps until all the sa mple data are written to or read from the internal ram. (6).write the scaling data to scal[5:0] bits ( tcf2, 04h... ) to scale the amplitude of the waveform based on the selected standard pulse amplitude when more than one ui is used to compose the pulse template, the over- lap of two consecutive pulses coul d make the pulse amplitude overflow (exceed the maximum limitation) if t he pulse amplitude is not set properly. this overflow is captured by dac_ov_is bit ( ints1, 17h... ), and, if enabled by the dac_ov_im bit ( intm1, 12h... ), an interrupt will be gen- erated. the following tables give all the sample data based on the preset pulse templates and lbos in detail for reference. for preset pulse templates and lbos, scaling up/down against the pul se amplitude is not supported. 1. table-2 transmit waveform value for e1 75 ? 2. table-3 transmit waveform value for e1 120 ? 3. table-4 transmit waveform value for t1 0~133 ft 4. table-5 transmit waveform value for t1 133~266 ft 5. table-6 transmit waveform value for t1 266~399 ft 6. table-7 transmit waveform value for t1 399~533 ft 7. table-8 transmit waveform value for t1 533~655 ft 8. table-9 transmit waveform value for j1 0~655 ft 9. table-10 transmit waveform value for ds1 0 db lbo 10. table-11 transmit waveform value for ds1 -7.5 db lbo 11. table-12 transmit waveform value for ds1 -15.0 db lbo 12. table-13 transmit waveform value for ds1 -22.5 db lbo idt82v2084 ttipn tringn cable r load v out note: r load = 100 ? 5%
16 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-2 transmit waveform value for e1 75 ? sample ui 1 ui 2 ui 3 ui 4 1 0000000 0000000 0000000 0000000 2 0000000 0000000 0000000 0000000 3 0000000 0000000 0000000 0000000 4 0001100 0000000 0000000 0000000 5 0110000 0000000 0000000 0000000 6 0110000 0000000 0000000 0000000 7 0110000 0000000 0000000 0000000 8 0110000 0000000 0000000 0000000 9 0110000 0000000 0000000 0000000 10 0110000 0000000 0000000 0000000 11 0110000 0000000 0000000 0000000 12 0110000 0000000 0000000 0000000 13 0000000 0000000 0000000 0000000 14 0000000 0000000 0000000 0000000 15 0000000 0000000 0000000 0000000 16 0000000 0000000 0000000 0000000 scal[5:0] = 100001 (default), one step change of this value of scal[5:0] results in 3% scaling up/down against the pulse amplitude. table-3 transmit waveform value for e1 120 ? sample ui 1 ui 2 ui 3 ui 4 1 0000000 0000000 0000000 0000000 2 0000000 0000000 0000000 0000000 3 0000000 0000000 0000000 0000000 4 0001111 0000000 0000000 0000000 5 0111100 0000000 0000000 0000000 6 0111100 0000000 0000000 0000000 7 0111100 0000000 0000000 0000000 8 0111100 0000000 0000000 0000000 9 0111100 0000000 0000000 0000000 10 0111100 0000000 0000000 0000000 11 0111100 0000000 0000000 0000000 12 0111100 0000000 0000000 0000000 13 0000000 0000000 0000000 0000000 14 0000000 0000000 0000000 0000000 15 0000000 0000000 0000000 0000000 16 0000000 0000000 0000000 0000000 scal[5:0] = 100001 (default), one step change of this value of scal[5:0] results in 3% scaling up/down against the pulse amplitude. table-4 transmit waveform value for t1 0~133 ft sample ui 1 ui 2 ui 3 ui 4 1 0010111 1000010 0000000 0000000 2 0100111 1000001 0000000 0000000 3 0100111 0000000 0000000 0000000 4 0100110 0000000 0000000 0000000 5 0100101 0000000 0000000 0000000 6 0100101 0000000 0000000 0000000 7 0100101 0000000 0000000 0000000 8 0100100 0000000 0000000 0000000 9 0100011 0000000 0000000 0000000 10 1001010 0000000 0000000 0000000 11 1001010 0000000 0000000 0000000 12 1001001 0000000 0000000 0000000 13 1000111 0000000 0000000 0000000 14 1000101 0000000 0000000 0000000 15 1000100 0000000 0000000 0000000 16 1000011 0000000 0000000 0000000 scal[5:0] = 110110 1 (default), one step change of this value of scal[5:0] results in 2% scaling up/down against the pulse amplitude. 1. in t1 mode, when arbitrary pulse for short haul application is configured, users should write ?110110? to scal[5:0] bits if no scaling is required. table-5 transmit waveform value for t1 133~266 ft sample ui 1 ui 2 ui 3 ui 4 1 0011011 1000011 0000000 0000000 2 0101110 1000010 0000000 0000000 3 0101100 1000001 0000000 0000000 4 0101010 0000000 0000000 0000000 5 0101001 0000000 0000000 0000000 6 0101000 0000000 0000000 0000000 7 0100111 0000000 0000000 0000000 8 0100110 0000000 0000000 0000000 9 0100101 0000000 0000000 0000000 10 1010000 0000000 0000000 0000000 11 1001111 0000000 0000000 0000000 12 1001101 0000000 0000000 0000000 13 1001010 0000000 0000000 0000000 14 1001000 0000000 0000000 0000000 15 1000110 0000000 0000000 0000000 16 1000100 0000000 0000000 0000000 see table-4
17 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-6 transmit waveform value for t1 266~399 ft sample ui 1 ui 2 ui 3 ui 4 1 0011111 1000011 0000000 0000000 2 0110100 1000010 0000000 0000000 3 0101111 1000001 0000000 0000000 4 0101100 0000000 0000000 0000000 5 0101011 0000000 0000000 0000000 6 0101010 0000000 0000000 0000000 7 0101001 0000000 0000000 0000000 8 0101000 0000000 0000000 0000000 9 0100101 0000000 0000000 0000000 10 1010111 0000000 0000000 0000000 11 1010011 0000000 0000000 0000000 12 1010000 0000000 0000000 0000000 13 1001011 0000000 0000000 0000000 14 1001000 0000000 0000000 0000000 15 1000110 0000000 0000000 0000000 16 1000100 0000000 0000000 0000000 see table-4 table-7 transmit waveform value for t1 399~533 ft sample ui 1 ui 2 ui 3 ui 4 1 0100000 1000011 0000000 0000000 2 0111011 1000010 0000000 0000000 3 0110101 1000001 0000000 0000000 4 0101111 0000000 0000000 0000000 5 0101110 0000000 0000000 0000000 6 0101101 0000000 0000000 0000000 7 0101100 0000000 0000000 0000000 8 0101010 0000000 0000000 0000000 9 0101000 0000000 0000000 0000000 10 1011000 0000000 0000000 0000000 11 1011000 0000000 0000000 0000000 12 1010011 0000000 0000000 0000000 13 1001100 0000000 0000000 0000000 14 1001000 0000000 0000000 0000000 15 1000110 0000000 0000000 0000000 16 1000100 0000000 0000000 0000000 see table-4 table-8 transmit waveform value for t1 533~655 ft sample ui 1 ui 2 ui 3 ui 4 1 0100000 1000011 0000000 0000000 2 0111111 1000010 0000000 0000000 3 0111000 1000001 0000000 0000000 4 0110011 0000000 0000000 0000000 5 0101111 0000000 0000000 0000000 6 0101110 0000000 0000000 0000000 7 0101101 0000000 0000000 0000000 8 0101100 0000000 0000000 0000000 9 0101001 0000000 0000000 0000000 10 1011111 0000000 0000000 0000000 11 1011110 0000000 0000000 0000000 12 1010111 0000000 0000000 0000000 13 1001111 0000000 0000000 0000000 14 1001001 0000000 0000000 0000000 15 1000111 0000000 0000000 0000000 16 1000100 0000000 0000000 0000000 see table-4 table-9 transmit waveform value for j1 0~655 ft sample ui 1 ui 2 ui 3 ui 4 1 0010111 1000010 0000000 0000000 2 0100111 1000001 0000000 0000000 3 0100111 0000000 0000000 0000000 4 0100110 0000000 0000000 0000000 5 0100101 0000000 0000000 0000000 6 0100101 0000000 0000000 0000000 7 0100101 0000000 0000000 0000000 8 0100100 0000000 0000000 0000000 9 0100011 0000000 0000000 0000000 10 1001010 0000000 0000000 0000000 11 1001010 0000000 0000000 0000000 12 1001001 0000000 0000000 0000000 13 1000111 0000000 0000000 0000000 14 1000101 0000000 0000000 0000000 15 1000100 0000000 0000000 0000000 16 1000011 0000000 0000000 0000000 scal[5:0] = 110110 (default), one step change of this value of scal[5:0] results in 2% scaling up/down against the pulse amplitude.
18 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-10 transmit waveform value for ds1 0 db lbo sample ui 1 ui 2 ui 3 ui 4 1 0010111 1000010 0000000 0000000 2 0100111 1000001 0000000 0000000 3 0100111 0000000 0000000 0000000 4 0100110 0000000 0000000 0000000 5 0100101 0000000 0000000 0000000 6 0100101 0000000 0000000 0000000 7 0100101 0000000 0000000 0000000 8 0100100 0000000 0000000 0000000 9 0100011 0000000 0000000 0000000 10 1001010 0000000 0000000 0000000 11 1001010 0000000 0000000 0000000 12 1001001 0000000 0000000 0000000 13 1000111 0000000 0000000 0000000 14 1000101 0000000 0000000 0000000 15 1000100 0000000 0000000 0000000 16 1000011 0000000 0000000 0000000 scal[5:0] = 110110 (default), one step change of this value results in 2% scaling up/down against the pulse amplitude. table-11 transmit waveform value for ds1 -7.5 db lbo sample ui 1 ui 2 ui 3 ui 4 1 0000000 0010100 0000010 0000000 2 0000010 0010010 0000010 0000000 3 0001001 0010000 0000010 0000000 4 0010011 0001110 0000010 0000000 5 0011101 0001100 0000010 0000000 6 0100101 0001011 0000001 0000000 7 0101011 0001010 0000001 0000000 8 0110001 0001001 0000001 0000000 9 0110110 0001000 0000001 0000000 10 0111010 0000111 0000001 0000000 11 0111001 0000110 0000001 0000000 12 0110000 0000101 0000001 0000000 13 0101000 0000100 0000000 0000000 14 0100000 0000100 0000000 0000000 15 0011010 0000011 0000000 0000000 16 0010111 0000011 0000000 0000000 scal[5:0] = 010001 (default), one step change of this value of scal[5:0] results in 6.25% scaling up/down against the pulse amplitude. table-12 transmit waveform value for ds1 -15.0 db lbo sample ui 1 ui 2 ui 3 ui 4 1 0000000 0110101 0001111 0000011 2 0000000 0110011 0001101 0000010 3 0000000 0110000 0001100 0000010 4 0000001 0101101 0001011 0000010 5 0000100 0101010 0001010 0000010 6 0001000 0100111 0001001 0000001 7 0001110 0100100 0001000 0000001 8 0010100 0100001 0000111 0000001 9 0011011 0011110 0000110 0000001 10 0100010 0011100 0000110 0000001 11 0101010 0011010 0000101 0000001 12 0110000 0010111 0000101 0000001 13 0110101 0010101 0000100 0000001 14 0110111 0010100 0000100 0000000 15 0111000 0010010 0000011 0000000 16 0110111 0010000 0000011 0000000 scal[5:0] = 001000 (default), one step change of the value of scal[5:0] results in 12.5% scaling up/down against the pulse amplitude. table-13 transmit waveform value for ds1 -22.5 db lbo sample ui 1 ui 2 ui 3 ui 4 1 0000001 0110101 0011011 0000111 2 0000011 0110101 0011001 0000110 3 0000101 0110100 0010111 0000110 4 0001000 0110011 0010101 0000101 5 0001100 0110010 0010100 0000101 6 0010001 0110000 0010010 0000101 7 0010110 0101110 0010001 0000100 8 0011011 0101101 0010000 0000100 9 0100001 0101011 0001110 0000100 10 0100110 0101001 0001101 0000100 11 0101010 0100111 0001100 0000011 12 0101110 0100100 0001011 0000011 13 0110001 0100010 0001010 0000011 14 0110011 0100000 0001001 0000011 15 0110100 0011110 0001000 0000011 16 0110100 0011100 0001000 0000010 scal[5:0] = 000100 (default), one step change of this value of scal[5:0] results in 25% scaling up/down against the pulse amplitude.
19 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.2.4 transmit path line interface the transmit line interface consists of ttipn pin and tringn pin. the impedance matching can be realized by the internal impedance matching circuit or the external impedance matc hing circuit. if t_term[2] is set to ?0?, the internal impedance matching circ uit will be selected. in this case, the t_term[1:0] bits ( term, 1ah... ) can be set to choose 75 ? , 100 ? , 110 ? or 120 ? internal impedance of ttipn/tringn. if t_term[2] is set to ?1?, the internal impedance matching ci rcuit will be disabled. in this case, the external impedance matc hing circuit will be used to realize the imped- ance matching. for t1/j1 mode, the external impedance matching circuit for the transmitter is not supported. figure-8 shows the appropriate external components to connect with the cable for one channel. table-14 is the list of the recommended impedance matching for transmitter. the ttipn/tringn can be turned into high impedance globally by pull- ing thz pin to high or indivi dually by setting the thz bit ( tcf1, 03h... ) to ?1?. in this state, the internal transmit circuits are still active. besides, in the following cases, tt ipn/tringn will also become high impedance: ? loss of mclk: all ttipn/tringn pins become high impedance; ? loss of tclkn: corresponding ttipn/tringn become hz (excep- tions: remote loopback; transmit internal pattern by mclk); ? transmit path power down; ? after software reset; pin reset and power on. note : the precision of the resistors should be better than 1% 3.2.5 transmit path power down the transmit path can be powered dow n individually by setting the t_off bit ( tcf0, 02h... ) to ?1?. in this case, the ttipn/tringn pins are turned into high impedance. table-14 impedance matching for transmitter cable configuration internal termination external termination t_term[2:0] puls[3:0] r t t_term[2:0] puls[3:0] r t e1/75 ? 000 0000 0 ? 1xx 0001 9.4 ? e1/120 ? 001 0001 0001 t1/0~133 ft 010 0010 - - - t1/133~266 ft 0011 t1/266~399 ft 0100 t1/399~533 ft 0101 t1/533~655 ft 0110 j1/0~655 ft 011 0111 0 db lbo 010 1000 -7.5 db lbo 1001 -15.0 db lbo 1010 -22.5 db lbo 1011
20 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.3 receive path the receive path consists of receiv e internal termination, monitor gain, amplitude/wave shape detector, digital tuning controller, adaptive equalizer, data slicer, cdr (clock and data recovery), optional jitter attenuator, decoder and los/ais detector. refer to figure-7 . 3.3.1 receive internal termination the impedance matching can be real ized by the internal impedance matching circuit or the external impedance matching circuit. if r_term[2] is set to ?0?, the internal impedance ma tching circuit will be selected. in this case, the r_term[1:0] bits ( term, 1ah... ) can be set to choose 75 ? , 100 ? , 110 ? or 120 ? internal impedance of rtipn/rringn. if r_term[2] is set to ?1?, the internal impedance ma tching circuit will be disabled. in this case, the external impedance matching ci rcuit will be used to realize the impedance matching. figure-8 shows the appropriate exter nal components to connect with the cable for one channel. table-15 is the list of the recommended imped- ance matching for receiver. figure-7 receive path function block diagram figure-8 transmit/receive line circuit table-15 impedance matching for receiver cable configuration internal te rmination external termination r_term[2:0] r r r_term[2:0] r r e1/75 ? 000 120 ? 1xx 75 ? e1/120 ? 001 120 ? t1 010 100 ? j1 011 110 ? monitor gain adaptive equalizer los/ais detector data slicer decoder los rclk rdp rdn rtip clock and data recovery receive internal termination rring jitter attenuator ? ? ?? r x line r r ? ? t x line r t r t rtipn rringn tringn ttipn idt82v2084 one of the four identical channels vddtn vddtn d4 d3 d2 d1 1 : 1 2 : 1 a b d6 d5 d8 d7 cp vddrn vddrn 2 3 ? 0.1 f gndtn vddtn 68 f 1 3.3 v ? 0.1 f gndrn vddrn 68 f 3.3 v 1 note : 1. common decoupling capacitor 2. cp 0-560 (pf) 3. d1 - d8, motorola - mbr0540t1; international rectifier - 11dq04 or 10bq060 ? ? ? ?
21 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.3.2 line monitor in both t1/j1 and e1 short haul applic ations, the non-intrusive monitor- ing on channels located in other chips can be performed by tapping the mon- itored channel through a high impedanc e bridging circuit. refer to figure- 9 and figure-10 . after a high resistance bridging circui t, the signal arriving at the rtipn/ rringn is dramatically attenuated. to compensate this attenuation, the monitor gain can be used to boost the signal by 22 db, 26 db and 32 db, selected by mg[1:0] bits ( rcf2, 09h... ). for normal operation, the monitor gain should be set to 0 db. figure-9 monitoring receive line in another chip figure-10 monitor transmit line in another chip 3.3.3 adaptive equalizer the adaptive equalizer can remove most of the signal distortion due to intersymbol interference caused by cable attenuation. it can be enabled or disabled by setting eq_on bit to ?1? or ?0? ( rcf1, 08h... ). when the adaptive equalizer is out of range, eq_s bit ( stat0, 14h... ) will be set to ?1? to indicate the status of equalizer. if eq_ies bit ( intes, 13h... ) is set to ?1?, any changes of eq _s bit will generate an interrupt and eq_is bit ( ints0, 16h... ) will be set to ?1? if it is not masked. if eq_ies bit is set to ?0?, only the ?0? to ?1? transit ion of the eq_s bit will generate an inter- rupt and eq_is bit will be set to ?1? if it is not masked. the eq_is bit will be reset after being read. the amplitude/wave shape detector keeps on measuring the ampli- tude/wave shape of the incoming signal s during an observation period. this observation period can be 32, 64, 128 or 256 symbol periods, as selected by updw[1:0] bits ( rcf2, 09h... ). a shorter observation period allows quicker response to pulse amplitude variation while a longer observation period can minimize the possible overshoots. the default observation period is 128 symbol periods. based on the observed peak value for a period, the equalizer will be adjusted to achieve a normali zed signal. latt[4:0] bits ( stat1, 15h... ) indicate the signal attenuation introduc ed by the cable in approximately 2 db per step. 3.3.4 receive sensitivity for short haul application, the receive sensitivity for both e1 and t1/ j1 is -10 db. for long haul application, the receive sensitivity is -43 db for e1 and -36 db for t1/j1. 3.3.5 data slicer the data slicer is used to generate a standard amplitude mark or a space according to the amplitude of the input signals. the threshold can be 40%, 50%, 60% or 70%, as selected by the slice[1:0] bits ( rcf2, 09h... ). the output of the data slicer is forwarded to the cdr (clock & data recovery) unit or to the rdpn/rdnn pi ns directly if the cdr is disabled. 3.3.6 cdr (clock & data recovery) the cdr is used to recover the clock from the received signals. the recovered clock tracks the jitter in th e data output from the data slicer and keeps the phase relationship betw een data and clock during the absence of the incoming pulse. the cdr can also be by-passed in the dual rail mode. when cdr is by-passed, the data from the data slicer is output to the rdpn/rdnn pins directly. 3.3.7 decoder in t1/j1 applications, the r_md[1:0] bits ( rcf0, 07h... ) is used to select the ami decoder or b8zs decoder. in e1 applications, the r_md[1:0] bits ( rcf0, 07h... ) are used to select the ami decoder or hdb3 decoder. 3.3.8 receive path system interface the receive path system interface consists of rclkn pin, rdn/rdpn pin and rdnn pin. in e1 mode, the rclkn outputs a recovered 2.048 mhz clock. in t1/j1 mode, the rclkn outputs a recovered 1.544 mhz clock. the received data is updated on the rdn/rdpn and rdnn pins on the active edge of rclkn. the active edge of rclkn can be selected by the rclk_sel bit ( rcf0, 07h... ). and the active level of the data on rdn/ rdpn and rdnn can also be se lected by the rd_inv bit ( rcf0, 07h... ). the received data can be output to the system side in two different ways: single rail or dual rail, as selected by r_md bit [1] ( rcf0, 07h... ). in sin- gle rail mode, only rdn pin is used to output data and the rdnn/cvn pin is used to report the received errors. in dual rail mode, both rdpn pin and rdnn pin are used for outputting data. in the receive dual rail mode, t he cdr unit can be by-passed by setting r_md[1:0] to ?11? (binary). in this situation, the output data from the data slicer will be output to the rdpn/ rdnn pins directly, and the rclkn out- puts the exclusive or (xor) of the rdpn and rdnn. 3.3.9 receive path power down the receive path can be powered dow n individually by setting r_off bit ( rcf0, 07h... ) to ?1?. in this case, the rclkn, rdn/rdpn, rdpn and losn will be logic low. rtip rring rtip rring normal receive mode monitor mode dsx cross connect point r monitor gain =22/26/32db monitor gain=0db ttip tring rtip rring normal transmit mode monitor mode dsx cross connect point r monitor gain monitor gain =22/26/32db
22 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.3.10 g.772 non-intrusive monitoring in applications using only three c hannels, channel 1 can be configured to monitor the data received or transmitted in any one of the remaining chan- nels. the mon[3:0] bits ( gcf1, 60h ) determine which channel and which direction (transmit/receive) will be m onitored. the monitoring is non-intru- sive per itu-t g.772. figure-11 illustrates the concept. the monitored line signal (transmi t or receive) goes through channel 1's clock and data recovery. the signal can be observed digitally at the rclk1, rd1/rdp1 and rdn1. if channel 1 is configured to remote loop- back while in the monitoring mode, the monitored data will be output on ttip1/tring1. figure-11 g.772 monitoring diagram channel n (n > 2) b8zs/ hdb3/ami encoder jitter attenuator line driver waveform shaper/lbo b8zs/ hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detector clock and data recovery transmitter internal termination receiver internal termination tclkn tdnn tdn/tdpn rclkn cvn/rdnn losn rdn/rdpn rringn ttipn tringn rtipn channel 1 b8zs/ hdb3/ami encoder jitter attenuator line driver waveform shaper/lbo b8zs/ hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detector clock and data recovery transmitter internal termination receiver internal termination tclk1 tdn1 tdn/tdp1 rclk1 cvn/rdn1 los1 rdn/rdp1 rring1 ttip1 tring1 rtip1 remote loopback g.772 monitor
23 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.4 jitter attenuator there is one jitter attenuator in each channel of the liu. the jitter atten- uator can be deployed in the transmit pat h or the receive path, and can also be disabled. this is selected by the jacf[1:0] bits ( jacf, 01h... ). 3.4.1 jitter attenuation function description the jitter attenuator is composed of a fifo and a dpll, as shown in figure-12 . the fifo is used as a pool to buffer the jittered input data, then the data is clocked out of the fifo by a de-jittered clock. the depth of the fifo can be 32 bits, 64 bits or 128 bits, as selected by the jadp[1:0] bits ( jacf, 01h... ). consequently, the constant delay of the jitter attenuator will be 16 bits, 32 bits or 64 bits. deeper fifo can tolerate larger jitter, but at the expense of increasing data latency time. figure-12 jitter attenuator in e1 applications, the corner frequency of the dpll can be 0.9 hz or 6.8 hz, as selected by the jabw bit ( jacf, 01h... ). in t1/j1 applications, the corner frequency of the dpll can be 1.25 hz or 5.00 hz, as selected by the jabw bit ( jacf, 01h... ). the lower the corner frequency is, the longer time is needed to achieve synchronization. when the incoming data moves faster than the outgoing data, the fifo will overflow. this overflow is captured by the jaov_is bit ( ints1, 17h... ). if the incoming data moves slower than the outgoing data, the fifo will underflow. this underflow is captured by the jaud_is bit ( ints1, 17h... ). for some applications that are sensit ive to data corruption, the ja limit mode can be enabled by setting ja_limit bit ( jacf, 01h... ) to ?1?. in the ja limit mode, the speed of the out going data will be adjusted automatically when the fifo is close to its full or emptiness. the criteria of starting speed adjustment are shown in table-16 . the ja limit mode can reduce the pos- sibility of fifo overflow and underflow, but the quality of jitter attenuation is deteriorated. 3.4.2 jitter attenuator performance the performance of the jitter attenuator in the idt82v2084 meets the itu-t i.431, g.703, g.736-739, g.823, g.824, etsi 300011, etsi tbr12/ 13, at&t tr62411 specifications. deta ils of the jitter attenuator perfor- mance is shown in table-68 jitter tolerance and table-69 jitter attenuator characteristics . fifo 32/64/128 dpll jittered data de-jittered data jittered clock de-jittered clock mclk w r rclkn rdn/rdpn rdnn table-16 criteria of starting speed adjustment fifo depth criteria for adjusting data outgoing speed 32 bits 2 bits close to its full or emptiness 64 bits 3 bits close to its full or emptiness 128 bits 4 bits close to its full or emptiness
24 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.5 los and ai s detection 3.5.1 los detection the loss of signal detector monitors the amplitude of the incoming sig- nal level and pulse density of the received signal on rtipn and rringn. ? los declare (los=1) a los is detected when the incoming signal has ?no transitions?, i.e., when the signal level is less than q db below nominal for n consecutive pulse intervals. here n is defined by lac bit ( maint0, 0ah... ). los will be declared by pulling losn pin to high (los=1) and los interrupt will be gen- erated if it is not masked. ? los clear (los=0) the los is cleared when the incoming signal has ?transitions?, i.e., when the signal level is greater than p db below nominal and has an aver- age pulse density of at least 12.5% for m consecutive pulse intervals, start- ing with the receipt of a pulse. here m is defined by lac bit ( maint0, 0ah... ). los status is cleared by pulling losn pin to low. figure-13 los declare and clear ? los detect level threshold in short haul mode, the amplitude threshold q is fixed on 800 mvpp, while p=q+200 mvpp (200 mvpp is the los level detect hysteresis). in long haul mode, the value of q can be selected by los[4:0] bit ( rcf1, 08h... ), while p=q+4 db (4 db is the los level detect hysteresis). the los[4:0] default value is 10101 (-46 db). ? criteria for declare and clear of a los detect the detection supports the ansi t1.231 and i.431 for t1/j1 mode and g.775 and etsi 300233/i.431 for e1 mode. the criteria can be selected by lac bit ( maint0, 0ah... ) and t1e1 bit (gcf0, 40h) . table-17 and table-18 summarize los declare and clear criteria for both short haul and long haul application. ? all ones output during los on the system side, the rdpn/rdnn wi ll reflect the input pulse ?transi- tion? at the rtipn/rringn side and out put recovery clock (but the quality of the output clock can not be guaranteed when the input level is lower than the maximum receive sensitivity) when aise bit ( maint0, 0ah... ) is 0; or output all ones as ais when aise bit ( maint0, 0ah... ) is 1. in this case rclkn output is replaced by mclk. on the line side, the ttipn/tringn will output all ones as ais when atao bit ( maint0, 0ah... ) is 1. the all ones pattern uses mclk as the reference clock. los indicator is always active for all kinds of loopback modes. signal levelp density=ok los=1 los=0 table-17 los declare and clear criteria for short haul mode control bit los declare threshold los clear threshold t1e1 lac 1=t1/j1 0=t1.231 level < 800 mvpp n=175 bits level > 1 vpp m=128 bits 12.5% mark density <100 consecutive zeroes 1=i.431 level < 800 mvpp n=1544 bits level > 1 vpp m=128 bits 12.5% mark density <100 consecutive zeroes 0=e1 0=g.775 level < 800 mvpp n=32 bits level > 1 vpp m=32 bits 12.5% mark density <16 consecutive zeroes 1=i.431/etsi level < 800 mvpp n=2048 bits level > 1 vpp m=32 bits 12.5% mark density <16 consecutive zeroes
25 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.5.2 ais detection the alarm indication signal can be detected by the idt82v2084 when the clock&data recovery unit is enabled. the status of ais detection is reflected in the ais_s bit ( stat0, 14h...) . in t1/j1 applications, the criteria for declaring/clearing ais detection are in compliance with the ansi t1.231. in e1 applications, the criter ia for declaring/clearing ais detection comply with the itu g.775 or the etsi 300233, as selected by the lac bit ( maint0, 0ah... ). table-19 summarizes different criteria for ais detection declaring/clearing. table-18 los declare and clear criteria for long haul mode control bit los declare thres hold los clear threshold note t1e1 lac los[4:0] q (db) 1=t1/j1 0 t1.231 00000 00001 ? 10001 ? 10101 10110-11111 -4 -6 ? -38 ? -46 -48 level < q n=175 bits level > q+ 4db m=128 bits 12.5% mark density <100 consecutive zeroes 1 - 00000 ? 00110 -4 -16 level < q n=1544 bits level > q+ 4db m=128 bits 12.5% mark density <100 consecutive zeroes i.431 level detect range is -18 to -30 db. i.431 00111 ? 01101 -18 ? -30 - 01110 ? 10001 ? 10101 10110-11111 -32 ? -38 ? -46 -48 0=e1 0 - 00000 ? 00010 -4 ? -8 level < q n=32 bits level > q+ 4db m=32 bits 12.5% mark density <16 consecutive zeroes g.775 level detect range is -9 to -35 db. g.775 00011 ? 10000 -10 ? -36 - 10001 ? 10101(default) 10110-11111 -38 ? -46 -48 1 - 00000 -4 level < q n=2048 bits level > q+ 4db m=32 bits 12.5% mark density <16 consecutive zeroes i.431 level detect range is -6 to -20 db. i.431/ etsi 00001 ? 01000 -6 ? -20 - 01001 ? 10101(default) 10110-11111 -22 ? -46 -48 table-19 ais condition itu g.775 for e1 (lac bit is set to ?0? by default) etsi 300233 for e1 (lac bit is set to ?1?) ansi t1.231 for t1/j1 ais detected less than 3 zeros contained in each of two consecutive 512-bit streams are received less than 3 zeros contained in a 512-bit stream are received less than 9 zeros contained in an 8192-bit stream (a ones density of 99.9% over a period of 5.3ms) ais cleared 3 or more zeros contained in each of two consecutive 512-bit streams are received 3 or more zeros contained in a 512-bit stream are received 9 or more zeros contained in an 8192-bit stream are received
26 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.6 transmit and detect internal patterns the internal patterns (all ones, all zeros, prbs/qrss pattern and activate/deactivate loopback code) wi ll be generated and detected by the idt82v2084. tclkn is used as the refe rence clock by default. mclk can also be used as the reference cl ock by setting the patt_clk bit ( maint0, 0ah... ) to ?1?. if the patt_clk bit ( maint0, 0ah... ) is set to ?0? and the patt[1:0] bits ( maint0, 0ah... ) are set to ?00?, the transmit path will operate in normal mode. 3.6.1 transmit all ones in transmit direction, the all ones data can be inserted into the data stream when the patt[1:0] bits ( maint0, 0ah... ) are set to ?01?. the trans- mit data stream is output from ttipn/ tringn. in this case, either tclkn or mclk can be used as the transmit clock, as selected by the patt_clk bit ( maint0, 0ah... ). 3.6.2 transmit all zeros if the patt_clk bit ( maint0, 0ah... ) is set to ?1?, the all zeros will be inserted into the transmit data stream when the patt[1:0] bits ( maint0, 0ah... ) are set to ?00?. 3.6.3 prbs/qrss generation and detection a prbs/qrss will be generated in the transmit direction and detected in the receive direction by idt82v2084. the qrss is 2 20 -1 for t1/j1 appli- cations and the prbs is 2 15 -1 for e1 applications, with maximum zero restrictions according to the at&t tr62411 and itu-t o.151. when the patt[1:0] bits ( maint0, 0ah... ) are set to ?10?, the prbs/ qrss pattern will be inserted into the transmit data stream with the msb first. the prbs/qrss pattern will be transmitted directly or invertedly. the prbs/qrss in the received data st ream will be monitored. if the prbs/qrss has reached synchroniza tion status, the prbs_s bit ( stat0, 14h... ) will be set to ?1?, even in the presence of a logic error rate less than or equal to 10 -1 . the criteria for setting/clearing the prbs_s bit are shown in table-20 . prbs data can be inverted through setting the prbs_inv bit ( maint0, 0ah... ). any change of prbs_s bit will be captured by prbs_is bit ( ints0, 16h... ). the prbs_ies bit ( intes, 13h... ) can be used to determine whether the ?0? to ?1? change of prbs_ s bit will be captured by the prbs_is bit or any changes of prbs_s bit will be captured by the prbs_is bit. when the prbs_is bit is ?1?, an interrupt will be generated if the prbs_im bit ( intm0, 11h... ) is set to ?1?. the received prbs/qrss logic errors can be counted in a 16-bit counter if the err_sel [1:0] bits ( maint6, 10h... ) are set to ?00?. refer to refer to 3.8 error detection/counting and insertion for the operation of the error counter. 3.7 loopback to facilitate testing and diagnosis, the idt82v2084 provides four dif- ferent loopback configurations : analog loopback, digital loopback, remote loopback and inband loopback. 3.7.1 analog loopback when the alp bit ( maint1, 0bh... ) is set to ?1?, the corresponding chan- nel is configured in analog loopback mode. in this mode, the transmit sig- nals are looped back to the receiver in ternal termination in the receive path then output from rclkn, rdn, rdpn/rdnn. at the same time, the transmit signals are still output to tt ipn/tringn in transmit direction. fig- ure-14 shows the process. 3.7.2 digital loopback when the dlp bit ( maint1, 0bh... ) is set to ?1?, the corresponding chan- nel is configured in digital loopback m ode. in this mode, the transmit sig- nals are looped back to the jitter attenuator (if enabled) and decoder in receive path, then output from rclkn, rdn, rdpn/rdnn. at the same time, the transmit signals are still output to ttipn/tringn in transmit direc- tion. figure-15 shows the process. both analog loopback mode and digital loopback mode allow the sending of the internal patterns (all o nes, all zeros, prbs, etc.) which will overwrite the transmit signals. in this case, either tclkn or mclk can be used as the reference clock for internal patterns transmission. 3.7.3 remote loopback when the rlp bit ( maint1, 0bh... ) is set to ?1?, the corresponding chan- nel is configured in remote loopback mode. in this mode, the recovered clock and data output from clock and data recovery on the receive path is looped back to the jitter attenuator (if enabled) and waveform shaper in transmit path. figure-16 shows the process. table-20 criteria for setting/clearing the prbs_s bit prbs/qrss detection 6 or less than 6 bit errors detected in a 64 bits hopping window. prbs/qrss missing more than 6 bit errors detected in a 64 bits hopping window.
27 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit figure-14 analog loopback figure-15 digital loopback figure-16 remote loopback one of the four identical channels b8zs/ hdb3/ami encoder jitter attenuator line driver waveform shaper/lbo b8zs/ hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detector clock and data recovery transmitter internal termination receiver internal termination tclkn tdnn tdn/tdpn rclkn cvn/rdnn losn rdn/rdpn rringn ttipn tringn rtipn analog loopback one of the four identical channels b8zs/ hdb3/ami encoder jitter attenuator b8zs/ hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detector clock and data recovery digital loopback receiver internal termination tclkn tdnn tdn/tdpn rclkn cvn/rdnn losn rdn/rdpn rringn ttipn tringn rtipn line driver waveform shaper/lbo transmitter internal termination one of the four identical channels b8zs/ hdb3/ami encoder jitter attenuator b8zs/ hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detector clock and data recovery receiver internal termination tclkn tdnn tdn/tdpn rclkn cvn/rdnn losn rdn/rdpn rringn ttipn tringn rtipn remote loopback line driver waveform shaper/lbo transmitter internal termination
28 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.7.4 inband loopback when patt[1:0] bits ( maint0, 0ah... ) are set to ?11?, the correspond- ing channel is configured in inband loopback mode. in this mode, an unframed activate/deactivate loopback code is generated repeatedly in transmit direction per ansi t1. 403 which overwrite the transmit signals. in receive direction, the framed or unframed code is detected per ansi t1. 403, even in the presence of 10 -2 bit error rate. if the automatic remote loopback is enabled by setting arlp bit ( maint1, 0bh... ) to ?1?, the chip will establish/demolish the remote loop- back based on the reception of the activate loopback code/deactivate loopback code for 5.1 s. if the arlp bit ( maint1, 0bh...) is set to ?0?, the remote loopback can also be demolished forcedly. 3.7.4.1 transmit activate/deactivate loopback code the pattern of the transmit activate/deactivate loopback code is defined by the tiblb[7:0] bits ( maint3, 0dh... ). whether the code repre- sents an activate loopback code or a deactivate loopback code is judged by the far end receiver. the length of the pattern ranges from 5 bits to 8 bits, as selected by the tiblb_l[1:0] bits ( maint2, 0ch... ). the pattern can be programmed to 6-bit-long or 8-bit-long respectively by repeating itself if it is 3-bit-long or 4-bit-long. when the patt[1:0] bits ( maint0, 0ah... ) are set to ?11?, the transmission of the activate/deactivate loopback code is initiated. if the patt_clk bit ( maint0, 0ah... ) is set to ?0? and the patt[1:0] bits ( maint0, 0ah... ) are set to ?00?, the transmission of the acti- vate/deactivate loopback code will stop. the local transmit activate/deacti vate code setting should be the same as the receive code setting in the remote end. it is the same thing for the other way round. 3.7.4.2 receive activate/deactivate loopback code the pattern of the receive acti vate loopback code is defined by the riblba[7:0] bits ( maint4, 0eh... ). the length of this pattern ranges from 5 bits to 8 bits, as selected by the riblba_l [1:0] bits ( maint2, 0ch... ). the pattern can be programmed to 6-bi t-long or 8-bit-l ong respectively by repeating itself if it is 3-bit-long or 4-bit-long. the pattern of the receive deactivate loopback code is defined by the riblbd[7:0] bits ( maint5, 0fh... ). the length of the receive deactivate loopback code ranges from 5 bits to 8 bits, as selected by the riblbd_l[1:0] bits ( maint2, 0ch... ). the pattern can be programmed to 6-bit-long or 8-bit-long respec tively by repeating itself if it is 3-bit-long or 4- bit-long. after the activate loopback code has been detected in the receive data for more than 30 ms (in e1 mode) / 40 ms (in t1/j1 mode), the iblba_s bit ( stat0, 14h... ) will be set to ?1? to declare the reception of the activate loopback code. after the deactivate loopback code has been detected in the receive data for more than 30 ms (in e1 mode) / 40 ms (in t1/j1 mode), the iblbd_s bit ( stat0, 14h... ) will be set to ?1? to declare the reception of the deactivate loopback code. when the iblba_ies bit ( intes, 13h... ) is set to ?0?, only the ?0? to ?1? transition of the iblba_s bit will generate an interrupt and set the iblba_is bit ( ints0, 16h... ) to ?1?. when the iblba_ies bit is set to ?1?, any changes of the iblba_s bit will generate an interrupt and set the iblba_is bit ( ints0, 16h... ) to ?1?. the iblba_is bit will be reset to ?0? after being read. when the iblbd_ies bit ( intes, 13h... ) is set to ?0?, only the ?0? to ?1? transition of the iblbd_s bit will generate an interrupt and set the iblbd_is bit ( ints0, 16h... ) to ?1?. when the iblbd_ies bit is set to ?1?, any changes of the iblbd_s bit will generate an interrupt and set the iblbd_is bit ( ints0, 16h... ) to ?1?. the iblbd_is bit will be reset to ?0? after being read. 3.7.4.3 automatic remote loopback when arlp bit ( maint1, 0bh...) is set to ?1?, the corresponding chan- nel is configured into the automatic remote loopback mode. in this mode, if the activate loopback code has been detected in the receive data for more than 5.1 s, the remote loopback (shown as figure-16 ) will be estab- lished automatically, and the rlp_s bit ( stat1, 15h... ) will be set to ?1? to indicate the establishment of the remote loopback. the iblba_s bit ( stat0, 14h... ) is set to ?1? to generate an interrupt. in this case, the remote loopback mode will still be kept even if the receiver stop receiving the acti- vate loopback code. if the deactivate loopback code has been detected in the receive data for more than 5.1 s, the remote loopback will be demolished automatically, and the rlp_s bit ( stat1, 15h... ) will set to ?0? to indicate the demolish- ment of the remote loopback. the iblbd_s bit ( stat0, 14h... ) is set to ?1? to generate an interrupt. the remote loopback can also be demolished forcedly by setting arlp bit ( maint1, 0bh...) to ?0?.
29 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.8 error detection/co unting and insertion 3.8.1 definition of line coding error the following line encoding errors can be detected and counted by the idt82v2084: ? received bipolar violation (bpv) error: in ami coding, when two consecutive pulses of the same pol arity are received, a bpv error is declared. ? hdb3/b8zs code violation (cv) error: in hdb3/b8zs coding, a cv error is declared when tw o consecutive bpv errors are detected, and the pulses that have the same polarity as the previ- ous pulse are not the hdb3/b8zs zero substitution pulses. ? excess zero (exz) error: there are two standards defining the exz errors: ansi and fcc. the exz_def bit ( maint6, 10h... ) chooses which standard will be adopted by the corresponding channel to judge the exz error. table-21 shows definition of exz. 3.8.2 error detection and counting which type of the receiving errors (received cv/bpv errors, excess zero errors and prbs logic errors ) will be counted is determined by err_sel[1:0] bits ( maint6, 10h... ). only one type of receiving error can be counted at a time except that when the err_sel[1:0] bits are set to ?11?, both cv/bpv and exz errors will be detected and counted. the receiving errors are counted in an internal 16-bit error counter. once an error is detected, an error in terrupt which is indicated by corre- sponding bit in ( ints1, 17h... ) will be generated if it is not masked. this error counter can be operated in two modes: auto report mode and man- ual report mode, as selected by the cnt_md bit ( maint6, 10h... ). in sin- gle rail mode, once bpv or cv errors are detected, the cvn pin will be driven to high for one rclk period. ? auto report mode in auto report mode, the internal c ounter starts to count the received errors when the cnt_md bit ( maint6, 10h... ) is set to ?1?. a one-second timer is used to set the counting per iod. the received errors are counted within one second. if the one-second timer expires, the value in the internal counter will be transferred to ( cnt0, 18h... ) and ( cnt1, 19h... ), then the internal counter will be reset and start to count received errors for the next second. the errors occurred during the transfer will be accumulated to the next round. the expiration of the one- second timer will set tmov_is bit ( ints1, 17h... ) to ?1?, and will generate an interrupt if the timer_im bit ( intm1, 12h... ) is set to ?0?. the tmov_is bit ( ints1, 17h... ) will be cleared after the interrupt register is read. the content in the ( cnt0, 18h... ) and ( cnt1, 19h... ) should be read within the next second. if the counter over- flows, a counter overflow interrupt which is indicated by cnt_ov_is bit ( ints1, 17h... ) will be generated if it is not masked by cnt_im bit ( intm1, 12h... ). figure-17 auto report mode table-21 exz definition exz definition ansi fcc ami more than 15 consecutive 0s are detected more than 80 consecutive 0s are detected hdb3 more than 3 consecutive 0s are detected more than 3 consecutive 0s are detected b8zs more than 7 consecutive 0s are detected more than 7 consecutive 0s are detected one-second timer expired? counting auto report mode (cnt_md=1) bit tmov_is is set to '1' y n cnt0, cnt1 data in counter counter 0 read the data in cnt0, cnt1 within the next second next second repeats the same process bit tmov_is is cleared after the interrupt register is read
30 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit ? manual report mode in manual report mode, the internal error counter starts to count the received errors when the cnt_md bit (maint6, 10h...) is set to ?0?. when there is a ?0? to ?1? transition on the cnt_trf bit (maint6, 10h...) , the data in the counter will be transferred to (cnt0, 18h...) and (cnt1, 19h...) , then the counter will be reset. the errors occurred during the transfer will be accumulated to the next round. if the c ounter overflows, a counter overflow interrupt indicated by cnt_ov_is bit (ints1, 17h...) will be generated if it is not masked by cnt_im bit (intm1, 12h...) . figure-18 manual report mode note: 1. it is recommended that users should do the followings within next round of error counting: read the data in cnt0 and cnt1; reset cnt_trf bit for the next ?0? to ?1? transition on this bit. 3.8.3 bipolar violation and prbs error insertion only when three consecutive ?1?s are detected in the transmit data stream, will a ?0? to ?1? transition on the bpv_ins bit ( maint6, 10h... ) gen- erate a bipolar violation pulse, and the polarity of the second ?1? in the series will be inverted. a ?0? to ?1? transition on the eer_ins bit ( maint6, 10h... ) will generate a logic error during the prbs/qrss transmission. 3.9 line driver failure monitoring the transmit driver failure monito r can be enabled or disabled by setting dfm_off bit ( tcf1, 03h... ). if the transmit driv er failure monitor is enabled, the transmit driver failur e will be captured by df_s bit ( stat0, 14h... ). the transition of the df_s bit is reflected by df_is bit ( ints0, 16h... ), and, if enabled by df_im bit ( intm0, 11h... ), will generate an inter- rupt. when there is a short circuit on the ttipn/tringn port, the output cur- rent will be limited to 100 ma (typical) and an interrupt will be generated. a '0' to '1' transition on cnt_trf? counting manual report mode (cnt_md=0) cnt0, cnt1 data in counter counter 0 y n next round repeat the same process read the data in cnt0, cnt1 within next round 1 reset cnt_trf for the next '0' to '1' transition
31 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.10 mclk and tclk 3.10.1 master clock (mclk) mclk is an independent, free-running re ference clock. mclk is 1.544 mhz or 37.056 mhz for t1/j1 applicat ions and 2.048 mhz or 49.152 mhz in e1 mode. this reference clock is used to generate several internal ref- erence signals: ? timing reference for the integrated clock recovery unit. ? timing reference for the int egrated digital jitter attenuator. ? timing reference for microcontroller interface. ? generation of rclk signal during a loss of signal condition if ais is enabled. ? reference clock during a blue alar m transmit all ones (taos), all zeros, prbs/qrss and inband loopback patterns if it is selected as the reference clock. for atao and ais, mclk is always used as the reference clock. figure-19 shows the chip operation status in different conditions of mclk and tclkn. the missing of mclk will set all the four ttip/tring to high impedance state. 3.10.2 transmit clock (tclk) the tclkn is used to sample the transmit data on tdn/tdpn, tdnn. the active edge of tclkn can be selected by the tclk_sel bit ( tcf0, 02h... ). during transmit all ones, prbs/qrss patterns or inband loop- back code, either tclkn or mclk can be used as the reference clock. this is selected by the patt_clk bit ( maint0, 0ah... ). but for automatic transmit all ones and ais, only mclk is used as the reference clock and the patt_clk bit is ignored. in automatic transmit all ones condition, the atao bit ( maint0, 0ah ) is set to ?1?. in ais condi- tion, the aise bit ( maint0, 0ah ) is set to ?1?. if tclkn has been missing for more than 70 mclk cycles, tclk_los bit ( stat0, 14h... ) will be set, and the corresponding ttipn/tringn will become high impedance if this channel is not used for remote loopback or is not using mclk to transmit internal patterns (taos, all zeros, prbs and in-band loopback code). when tclkn is detected again, tclk_los bit ( stat0, 14h... ) will be cleared. the reference frequency to detect a tclkn loss is derived from mclk. figure-19 tclk operation flowchart normal operation mode transmitter n enters high impedance status and generates transmit clock loss interrupt if not masked tclkn status? clocked l/h mclk=h/l? all transmitters high impedance status yes clocked
32 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.11 microcontrol ler interfaces the microcontroller interface provi des access to read and write the reg- isters in the device. the chip suppor ts serial processor interface and two kinds of parallel processor interf ace: motorola non_multiplexed mode and intel non_multiplexed mode. by pulling pin p/ s to low or to high, the micro- controller interface can be set to wo rk in serial mode or in parallel mode respectively. refer to 7 microcontroller interface timing characteristics for details. 3.11.1 parallel microcontroller interface the interface is compatible with mo torola or intel microcontroller. pin int/ mot is used to select the operating m ode of the parallel microcontroller interface. when pin int/ mot is pulled to low, the parallel microcontroller interface is configured for motorola compatible hosts. when high, it is for intel compatible microcontrollers. 3.11.2 serial microcontroller interface the serial interface pins include sclk, sdi, sdo, cs as well as sclke (control pin for the selection of se rial clock active edge). by pulling p/ s pin to low, the device operates in the seri al host mode. in this mode, the reg- isters are programmed through a 24-bi t word which contains an 8-bit address byte (a0~a7), a subsequent 8-bit command byte (bit r/ w ) and an 8-bit data byte (d0~d7). when bit r/ w is ?1?, data is read out from pin sdo. when bit r/ w is ?0?, data is written into sdi pin. refer to figure-20 . figure-20 serial proces sor interface function timing a0 a1 a2 a3 a4 a5 a6 a7 r/ w d0 d1 d2 d3 d4 d5 d6 d7 cs sclk sdi address byte command byte input data byte (r/ w =0) d0 d1 d2 d3 d4 d5 d6 d7 remains high impedance sdo output data byte (r/ w =1) don't care
33 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 3.12 interrupt handling all kinds of interrupt of the idt82v2084 are indicated by the int pin. when the int_pin[0] bit ( gcf0, 40h ) is ?0?, the int pin is open drain active low, with a 10 k ? external pull-up resistor. when the int_pin[1:0] bits ( gcf0, 40h ) are ?01?, the int pin is push-pull active low; when the int_pin[1:0] bits are ?10?, the int pin is push-pull active high. all the interrupt can be disabled by the intm_glb bit ( gcf0, 40h ). when the intm_glb bit ( gcf0, 40h ) is set to ?0?, an active level on the int pin represents an interrupt of t he idt82v2084. the int_ch[7:0] bits ( intch, 80h ) should be read to identify which channel(s) generate the interrupt. the interrupt event is captured by the corresponding bit in the interrupt status register (ints0, 16h...) or (ints1, 17h...) . every kind of interrupt can be enabled/disabled individually by the corresponding bit in the register (intm0, 11h...) or (intm1, 12h...) . some event is reflected by the corre- sponding bit in the status register (stat0, 14h... ) or (stat1, 15h...) , and the interrupt trigger edge selection register can be used to determine how the status register sets the interrupt status register. after the interrupt status register (ints0, 16h...) or (ints1, 17h...) is read, the corresponding bit indicating which channel generates the inter- rupt in the intch register ( 80h ) will be reset. only when all the pending interrupt is acknowledged through readi ng the interrupt status registers of all the channels (ints0, 16h...) or (ints1, 17h...) will all the bits in the intch register ( 80h ) be reset and the int pin become inactive. there are totally fourteen kinds of events that could be the interrupt source for one channel: (1).los detected (2).ais detected (3).driver failure detected (4).tclk loss (5).synchronization status of prbs (6).prbs error detected (7).code violation received (8).excessive zeros received (9).ja fifo overflow/underflow (10).inband loopback code status (11).equalizer out of range (12).one-second timer expired (13).error counter overflow (14).arbitrary waveform generator overflow table-22 is a summary of all kinds of interrupt and their associated sta- tus bit, interrupt status bit, interrupt trigger edge selection bit and interrupt mask bit. 3.13 5v tolerant i/o pins all digital input pins will tolerate 5.0 5% volts and are compatible with ttl logic. 3.14 reset operation the chip can be reset in two ways: ? software reset: writing to the rst register ( 20h ) will reset the chip in 1 us. ? hardware reset: asserting the rst pin low for a minimum of 100 ns will reset the chip. after reset, all drivers output are in high impedance state, all the internal flip-flops are reset, and all the register s are initialized to default values. 3.15 power supply this chip uses a single 3.3 v power supply. table-22 interrupt event interrupt event status bit (stat0, stat1) interrupt status bit (ints0, ints1) interrupt edge selection bit (intes) interrupt mask bit (intm0, intm1) los detected los_s los_is los_ies los_im ais detected ais_s ais_is ais_ies ais_im driver failure detected df_s df_is df_ies df_im tclkn loss tclk_los tclk_los_is tclk_ies tclk_im synchronization status of prbs/qrss prbs_s prbs_is prbs_ies prbs_im prbs/qrss error err_is err_im code violation received cv_is cv_im excessive zeros received exz_is exz_im ja fifo overflow jaov_is jaov_im ja fifo underflow jaud_is jaud_im equalizer out of range eq_s eq_is eq_ies eq_im inband loopback activate code status iblba_s iblba_is iblba_ies iblba_im inband loopback deactivate code status iblbd_s iblbd_is iblbd_ies iblbd_im one-second timer expired tmov_is timer_im error counter overflow cnt_ov_is cnt_im arbitrary waveform generator overflow dac_ov_is dac_ov_im
34 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 4 programming information 4.1 register list and map the idt82v2084 registers can be di vided into global registers and local registers. the operation on the global registers affects all the four channels while the operation on local r egisters only affects that specific channel. for different channel, the address of local register is different. table-23 is the map of global registers and table-24 is the map of local registers. if the configuration of all the four channels is the same, the copy bit ( gcf0, 40h ) can be set to ?1? to establish the broadcasting mode. in the broadcasting mode, the writing operati on on any of the four channels? reg- isters will be copied to the corres ponding registers of all the other channels. table-23 global register list and map address (hex) register r/w map b7 b6 b5 b4 b3 b2 b1 b0 00 id r id7 id6 id5 id4 id3 id2 id1 id0 20 rst w 40 gcf0 r/w - - - t1e1 copy intm_glb int_pin1 int_pin0 60gcf1r/w mon3mon2mon1mon0 - - - - 80 intch r - int_ch4 - int_ch3 - int_ch2 - int_ch1 a0 reserved c0 reserved e0 reserved
35 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-24 per channel register list and map address (hex) register r/w map ch1-ch4 b7 b6 b5 b4 b3 b2 b1 b0 jitter attenuation control register 01,41,81,c1 jacf r/w - - ja_limit jacf1 jacf0 jadp1 jadp0 jabw transmit path control registers 02,42,82,c2 tcf0 r/w - - - t_off td_inv tclk_sel t_md1 t_md0 03,43,83,c3 tcf1 r/w - - dfm_off thz puls3 puls2 puls1 puls0 04,44,84,c4 tcf2 r/w - - scal5 scal4 scal3 scal2 scal1 scal0 05,45,85,c5 tcf3 r/w done rw ui1 ui0 samp3 samp2 samp1 samp0 06,46,86,c6 tcf4 r/w - wdat6 wdat5 wdat4 wdat3 wdat2 wdat1 wdat0 receive path control registers 07,47,87,c7 rcf0 r/w - - - r_of f rd_inv rclk_sel r_md1 r_md0 08,48,88,c8 rcf1 r/w - eq_on - los4 los3 los2 los1 los0 09,49,89,c9 rcf2 r/w - - slice1 slice0 updw1 updw0 mg1 mg0 network diagnostics control registers 0a,4a,8a,ca maint0 r/w - patt1 patt0 patt_clk prbs_inv lac aise atao 0b,4b,8b,cb maint1 - - - - arlp rlp alp dlp 0c,4c,8c,cc maint2 r/w - - tiblb_l1 tiblb_l0 riblba_l1 riblba_l0 riblbd_l1 riblbd_l0 0d,4d,8d,cd maint3 r/w tiblb7 tiblb6 ti blb5 tiblb4 tiblb3 tiblb2 tiblb1 tiblb0 0e,4e,8e,ce maint4 r/w riblba7 riblba6 riblba5 riblba4 riblba3 riblba2 riblba1 riblba0 0f,4f,8f,cf maint5 r/w riblbd7 riblbd6 riblbd5 riblbd4 riblbd3 riblbd2 riblbd1 riblbd0 10,50,90,d0 maint6 r/w - bpv_ins err_ins exz_def err_sel1 err_sel0 cnt_md cnt_trf interrupt control registers 11,51,91,d1 intm0 r/w eq_im iblba_im iblbd _im prbs_im tclk_im df_im ais_im los_im 12,52,92,d2 intm1 r/w dac_ov_im jaov_im jaud_im err_im exz_im cv_im timer_im cnt_im 13,53,93,d3 intes r/w eq_ies iblba_ies iblbd_i es prbs_ies tclk_ies df_ies ais_ies los_ies line status registers 14,54,94,d4 stat0 r eq_s iblba_s iblbd _s prbs_s tclk_los df_s ais_s los_s 15,55,95,d5 stat1 r - - rlp_s latt4 latt3 latt2 latt1 latt0 interrupt status registers 16,56,96,d6 ints0 r eq_is iblba_is iblbd_is prbs_is tclk_los_is df_is ais_is los_is 17,57,97,d7 ints1 r dac_ov_is jaov_is jaud_is err_is exz_is cv_is tmov_is cnt_ov_is counter registers 18,58,98,d8 cnt0 r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 19,59,99,d9 cnt1 r bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 transmit and receive termination registers 1a,5a,9a,da term r/w - - t_term2 t_term1 t_term0 r_term2 r_term1 r_term0
36 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 4.2 register description 4.2.1 global registers table-25 id: chip revision register (r, address = 00h) symbol bit default description id[7:0] 7-0 01h 00h is for the first version. table-26 rst: reset register (w, address = 20h) symbol bit default description rst[7:0] 7-0 01h software reset. a write operation on this register will reset all internal registers to their default values, and the sta- tus of all ports are set to the default status. the content in this register can not be changed. table-27 gcf0: global configuration register 0 (r/w, address = 40h) symbol bit default description -7-60reserved - 5 0 reserved. for normal operation, this bit should be set to ?0?. t1e1 4 0 this bit selects e1 or t1/j1 operation mode globally. = 0: e1 mode is selected. = 1: t1/j1 mode is selected. copy 3 0 enable broadcasting mode. = 0: broadcasting mode disabled = 1: broadcasting mode enabled. writing operation on one channel's register will be copied exactly to the corre- sponding registers in all the other channels. intm_glb 2 1 global interrupt enable = 0: interrupt is globally enabled. but for each individual interrupt, it still can be disabled by its corresponding inter- rupt mask bit. = 1: all the interrupts are disabled for all channels. int_pin[1:0] 1-0 00 interrupt pin operation mode selection = x0: open drain, active low (with an external pull-up resistor) = 01: push-pull, active low = 11: push-pull, active high
37 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 4.2.2 jitter attenuation control register table-28 gcf1: global configuration register 1 (r/w, address = 60h) symbol bit default description mon[3:0] 7-4 0000 mon selects the transmitter or receiver channel to be monitored. = 0000: receiver 1 is in normal operation without monitoring = 0001: reserved = 0010: monitor receiver 2 = 0011: reserved = 0100: monitor receiver 3 = 0101: reserved = 0110: monitor receiver 4 = 0111: reserved = 1000: transmitter 1 is in normal operation without monitoring = 1001: reserved = 1010: monitor transmitter 2 = 1011: reserved = 1100: monitor transmitter 3 = 1101: reserved = 1110: monitor transmitter 4 = 1111: reserved - 3-0 0000 reserved table-29 intch: interrupt channel in dication register (r, address = 80h) symbol bit default description int_ch[7:0] 7-0 00h int_ch[0, 2, 4 or 6]=1 indicates that an interrupt was generated by channel 1, 2, 3 or 4 respectively. table-30 jacf: jitter attenuator configuration register (r/w, address = 01h,41h,81h,c1h) symbol bit default description - 7-6 00 reserved ja_limit 5 0 wide jitter attenuation bandwidth = 0: normal mode = 1: ja limit mode jacf[1:0] 4-3 00 jitter attenuator configuration = 00/10: ja not used = 01: ja in transmit path = 11: ja in receive path jadp[1:0] 2-1 00 jitter attenuator depth selection = 00: 128 bits = 01: 64 bits = 10/11: 32 bits jabw 0 0 jitter transfer function bandwidth selection jabw t1/j1 e1 05 hz 6.8 hz 1 1.25 hz 0.9 hz
38 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 4.2.3 transmit path control registers 1. in internal impedance matching mode, for e1/75 ? cable impedance, the puls[3:0] bits ( tcf1, 03h... ) should be set to ?0000?. in external impedance matching mode, for e1/75 ? cable impedance, the puls[3:0] bits should be set to ?0001?. table-31 tcf0: transmitter configuration register 0 (r/w, address = 02h,42h,82h,c2h) symbol bit default description - 7-5 000 reserved t_off 4 0 transmitter power down enable = 0: transmitter power up = 1: transmitter power down and line driver high impedance td_inv 3 0 transmit data invert = 0: data on tdn or tdpn/tdnn is active high = 1: data on tdn or tdpn/tdnn is active low tclk_sel 2 0 transmit clock edge select = 0: data on tdn or tdpn/tdnn is sampled on the falling edges of tclkn = 1: data on tdn or tdpn/tdnn is sampled on the rising edges of tclkn t_md[1:0] 1-0 00 transmitter operation mode control bits which select different stages of transmit data path = 00: enable hdb3/b8zs encoder and waveform shaper blocks, input on tdn is single rail nrz data = 01: enable ami encoder and waveform shaper blocks, input on pin tdn is single rail nrz data = 1x: encoder is bypassed, dual rail nrz transmit data input on pin tdpn/tdnn table-32 tcf1: transmitter configuration register 1 (r/w, address = 03h,43h,83h,c3h) symbol bit default description - 7-6 00 reserved. this bit should be ?0? for normal operation. dfm_off 5 0 transmit driver failure monitor disable = 0: dfm is enabled = 1: dfm is disabled thz 4 1 transmit line driver high impedance enable = 0: normal state = 1: transmit line driver high impedance enable (other transmit path still in normal state) puls[3:0] 3-0 0000 these bits select the transmit template/lbo for short-haul/long-haul applications. t1/e1/j1 tclk cable impedance cable range or lbo cable loss 0000 1 e1 2.048 mhz 75 ? - 0~43 db (default) 0001 e1 2.048 mhz 120 ? -0~43 db 0010 dsx1 1.544 mhz 100 ? 0~133 ft 0~0.6 db 0011 dsx1 1.544 mhz 100 ? 133~266 ft 0.6~1.2 db 0100 dsx1 1.544 mhz 100 ? 266~399 ft 1.2~1.8 db 0101 dsx1 1.544 mhz 100 ? 399~533 ft 1.8~2.4 db 0110 dsx1 1.544 mhz 100 ? 533~655 ft 2.4~3.0 db 0111 j1 1.544 mhz 110 ? 0~655 ft 0~3.0 db 1000 ds1 1.544 mhz 100 ? 0 db lbo 0~36 db 1001 ds1 1.544 mhz 100 ? -7.5 db lbo 0~28.5 db 1010 ds1 1.544 mhz 100 ? -15 db lbo 0~21 db 1011 ds1 1.544 mhz 100 ? -22.5 db lbo 0~13.5 db 11xx user programmable waveform setting
39 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-33 tcf2: transmitter configuration register 2 (r/w, address = 04h,44h,84h,c4h) symbol bit default description - 7-6 00 reserved scal[5:0] 5-0 100001 scal specifies a scaling factor to be applied to the amplitude of the user-programmable arbitrary pulses whic h is to be transmitted if needed. the default value of scal[5:0] is ?100001?. refer to 3.2.3.3 user-programmable arbi- trary waveform . = 110110: default value for t1 0~133 ft, t1 133~266 ft, t1 266~399 ft, t1 399~533 ft, t1 533~655 ft, j1 0~655 ft, ds1 0db lbo. one step change of this value results in 2% scaling up/down against the pulse amplitude. = 010001: default value for ds1 -7.5 db lbo. one step change of this value results in 6.25% scaling up/down against the pulse amplitude. = 001000: default value for ds1 -15.0 db lbo. one step change of this value results in 12.5% scaling up/down against the pulse amplitude. = 000100: default value for ds1 -22.5 db lbo. one step change of this value results in 25% scaling up/down against the pulse amplitude. = 100001: default value for e1 75 ? and 120 ? . one step change of this value results in 3% scaling up/down against the pulse amplitude. table-34 tcf3: transmitter configuration register 3 (r/w, address = 05h,45h,85h,c5h) symbol bit default description done 7 0 after ?1? is written to this bit, a read or write operation is implemented. rw 6 0 this bit selects read or write operation = 0: write to ram = 1: read from ram ui[1:0] 5-4 00 these bits specify the unit interval address. there are 4 unit intervals. = 00: ui address is 0 (the most left ui) = 01: ui address is 1 = 10: ui address is 2 = 11: ui address is 3 samp[3:0] 3-0 0000 these bits specify the sample address. each ui has 16 samples. = 0000: sample address is 0 (the most left sample) = 0001: sample address is 1 = 0010: sample address is 2 ...... = 1110: sample address is 14 = 1111: sample address is 15 table-35 tcf4: transmitter configuration register 4 (r/w, address = 06h,46h,86h,c6h) symbol bit default description -70reserved wdat[6:0] 6-0 0000000 in indirect write operation, the wdat[6:0] will be loaded to the pulse template ram, specifying the amplitud e of the sample. after an indirect read operation, the amplitude data of the sample in the pulse template ram will be output to the wdat[6:0].
40 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 4.2.4 receive path control registers table-36 rcf0: receiver configuration register 0 (r/w, address = 07h,47h,87h,c7h) symbol bit default description - 7-5 000 reserved r_off 4 0 receiver power down enable = 0: receiver power up = 1: receiver power down rd_inv 3 0 receive data invert = 0: data on rdn or rdpn/rdnn is active high = 1: data on rdn or rdpn/rdnn is active low rclk_sel 2 0 receive clock edge select (this bit is ignored in slicer mode) = 0: data on rdn or rdpn/rdnn is updated on the rising edges of rclkn = 1: data on rdn or rdpn/rdnn is updated on the falling edges of rclkn r_md[1:0] 1-0 00 receiver path decoding selection = 00: receive data is hdb3 (e1) / b8zs (t1/j1) decoded and output on rdn with single rail nrz format = 01: receive data is ami decoded and output on rdn with single rail nrz format = 10: decoder is bypassed, re-timed dual rail data with nrz format output on rdpn/rdnn (dual rail mode with clock recovery) = 11: both cdr and decoder blocks are bypassed, slicer data with rz format output on rdpn/rdnn (slicer mode)
41 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-37 rcf1: receiver configuration register 1 (r/w, address = 08h,48h,88h,c8h) symbol bit default description -70reserved eq_on 6 0 = 0: receive equalizer off (short haul receiver) = 1: receive equalizer on (long haul receiver) - 5 0 reserved. should be 0 for normal operation. los[4:0] 4-0 10101 los clear level (db) los declare level (db) 00000 0 <-4 00001 >-2 <-6 00010 >-4 <-8 00011 >-6 <-10 00100 >-8 <-12 00101 >-10 <-14 00110 >-12 <-16 00111 >-14 <-18 01000 >-16 <-20 01001 >-18 <-22 01010 >-20 <-24 01011 >-22 <-26 01100 >-24 <-28 01101 >-26 <-30 01110 >-28 <-32 01111 >-30 <-34 10000 >-32 <-36 10001 >-34 <-38 10010 >-36 <-40 10011 >-38 <-42 10100 >-40 <-44 10101 >-42 <-46 10110-11111 >-44 <-48
42 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 4.2.5 network diagnost ics control registers table-38 rcf2: receiver configuration register 2 (r/w, address =09h,49h,89h,c9h) symbol bit default description - 7-6 00 reserved slice[1:0] 5-4 01 receive slicer threshold = 00: the receive slicer generates a mark if the voltage on rtipn/rringn exceeds 40% of the peak amplitude. = 01: the receive slicer generates a mark if the voltage on rtipn/rringn exceeds 50% of the peak amplitude. = 10: the receive slicer generates a mark if the voltage on rtipn/rringn exceeds 60% of the peak amplitude. = 11: the receive slicer generates a mark if the voltage on rtipn/rringn exceeds 70% of the peak amplitude. updw[1:0] 3-2 10 equalizer observation window = 00: 32 bits = 01: 64 bits = 10: 128 bits = 11: 256 bits mg[1:0] 1-0 00 monitor gain setting: these bits select the internal linear gain boost = 00: 0 db = 01: 22 db = 10: 26 db = 11: 32 db table-39 maint0: maintenance function control register 0 (r/w, address = 0ah,4ah,8ah,cah) symbol bit default description -70reserved patt[1:0] 6-5 00 these bits select the internal pattern and insert it into the transmit data stream. = 00: normal operation (patt_clk = 0) / insert all zeros (patt_clk = 1) = 01: insert all ones = 10: insert prbs (e1: 2 15 -1) or qrss (t1/j1: 2 20 -1) = 11: insert programmable inband loopback activate or deactivate code patt_clk 4 0 selects reference clock for transmitting internal pattern = 0: uses tclkn as the reference clock = 1: uses mclk as the reference clock prbs_inv 3 0 inverts prbs = 0: prbs data is not inverted = 1: prbs data is inverted before transmission and detection lac 2 0 the los/ais criterion is selected as below: = 0: g.775 (e1) / t1.231 (t1/j1) = 1: etsi 300233 & i.431 (e1) / i.431 (t1/j1) aise 1 0 ais enable during los = 0: ais insertion on rdpn/rdnn/rclkn is disabled during los = 1: ais insertion on rdpn/rdnn/rclkn is enabled during los atao 0 0 automatically transmit all ones (enabled only when patt[1:0] = 01) = 0: disabled = 1: automatically transmit all ones pattern at ttipn/tringn during los.
43 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-40 maint1: maintenance function control register 1 (r/w, address = 0bh,4bh,8bh,cbh) symbol bit default description - 7-4 0000 reserved arlp 3 0 automatic remote loopback control = 0: disables automatic remote loopback (normal transmit and receive operation) = 1: enables automatic remote loopback rlp 2 0 remote loopback enable = 0: disables remote loopback (normal transmit and receive operation) = 1: enables remote loopback alp 1 0 analog loopback enable = 0: disables analog loopback (normal transmit and receive operation) = 1: enables analog loopback dlp 0 0 digital loopback enable = 0: disables digital loopback (normal transmit and receive operation) = 1: enables digital loopback table-41 maint2: maintenance function control register 2 (r/w, address = 0ch,4ch,8ch,cch) symbol bit default description - 7-6 00 reserved. tiblb_l[1:0] 5-4 00 defines the length of the user-programmabl e transmit inband loopback activate/deactivate code contained in tiblb register. the default selection is 5 bits length. = 00: 5-bit activate code in tiblb [4:0] = 01: 6-bit activate code in tiblb [5:0] = 10: 7-bit activate code in tiblb [6:0] = 11: 8-bit activate code in tiblb [7:0] riblba_l[1:0] 3-2 00 defines the length of the user-programmable receive inband loopback activate code contained in riblba regis- ter. = 00: 5-bit activate code in riblba [4:0] = 01: 6-bit activate code in riblba [5:0] = 10: 7-bit activate code in riblba [6:0] = 11: 8-bit activate code in riblba [7:0] riblbd_l[1:0] 1-0 01 defines the length of the user-programmable receive inband loopback deactivate code contained in riblbd reg- ister. = 00: 5-bit deactivate code in riblbd [4:0] = 01: 6-bit deactivate code in riblbd [5:0] = 10: 7-bit deactivate code in riblbd [6:0] = 11: 8-bit deactivate code in riblbd [7:0] table-42 maint3: maintenance function control register 3 (r/w, address = 0dh,4dh,8dh,cdh) symbol bit default description tiblb[7:0] 7-0 (000)00001 defines the user-programmable transmit inband loopback activate/deactivate code. the default selection is 00001. tiblb[7:0] form the 8-bit repeating code tiblb[6:0] form the 7-bit repeating code tiblb[5:0] form the 6-bit repeating code tiblb[4:0] form the 5-bit repeating code
44 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-43 maint4: maintenance function control register 4 (r/w, address = 0eh,4eh,8eh,ceh) symbol bit default description riblba[7:0] 7-0 (000)00001 defines the user-programmable receive inband loopback activate code. the default selection is 00001. riblba[7:0] form the 8-bit repeating code riblba[6:0] form the 7-bit repeating code riblba[5:0] form the 6-bit repeating code riblba[4:0] form the 5-bit repeating code table-44 maint5: maintenance function control register 5 (r/w, address = 0fh,4fh,8fh,cfh) symbol bit default description riblbd[7:0] 7-0 (00)001001 defines the user-programmable receive inband loopback deactivate code. the default selection is 00100 1. riblbd[7:0] form the 8-bit repeating code riblbd[6:0] form the 7-bit repeating code riblbd[5:0] form the 6-bit repeating code riblbd[4:0] form the 5-bit repeating code table-45 maint6: maintenance function control register 6 (r/w, address = 10h,50h,90h,d0h) symbol bit default description - 7 0 reserved. bpv_ins 6 0 bpv error insertion a ?0? to ?1? transition on this bit will cause a single bipolar violation error to be inserted into the transmit data stream. this bit must be cleared and set again for a subsequent error to be inserted. err_ins 5 0 prbs/qrss logic error insertion a ?0? to ?1? transition on this bit will cause a single prbs/qrss logic error to be inserted into the transmit prbs/ qrss data stream. this bit must be cleared and set again for subsequent error to be inserted. exz_def 4 0 exz definition select = 0: ansi = 1: fcc err_sel 3-2 00 these bits choose which type of error will be counted = 00: the prbs logic error is counted by a 16-bit error counter. = 01: the exz error is counted by a 16-bit error counter. = 10: the received cv (bpv) error is counted by a 16-bit error counter. = 11: both cv (bpv) and exz errors ar e counted by a 16-bit error counter. cnt_md 1 0 counter operation mode select = 0: manual report mode = 1: auto report mode cnt_trf 0 0 = 0: clear this bit for the next ?0? to ?1? transition on this bit. = 1: error counting result is transferred to cnt0 and cnt1 and the error counter is reset.
45 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 4.2.6 interrupt control registers table-46 intm0: interrupt mask register 0 (r/w, address = 11h,51h,91h,d1h) symbol bit default description eq_im 7 1 equalizer out of range interrupt mask = 0: equalizer out of range interrupt enabled = 1: equalizer out of range interrupt masked iblba_im 6 1 in-band loopback activate code detect interrupt mask = 0: in-band loopback activate code detect interrupt enabled = 1: in-band loopback activate code detect interrupt masked iblbd_im 5 1 in-band loopback deactivate code detect interrupt mask = 0: in-band loopback deactivate code detect interrupt enabled = 1: in-band loopback deactivate code detect interrupt masked prbs_im 4 1 prbs synchronic signal detect interrupt mask = 0: prbs synchronic signal detect interrupt enabled = 1: prbs synchronic signal detect interrupt masked tclk_im 3 1 tclk loss detect interrupt mask = 0: tclk loss detect interrupt enabled = 1: tclk loss detect interrupt masked df_im 2 1 driver fail ure interrupt mask = 0: driver failure interrupt enabled = 1: driver failure interrupt masked ais_im 1 1 alarm indication signal interrupt mask = 0: alarm indication signal interrupt enabled = 1: alarm indication signal interrupt masked los_im 0 1 loss of signal interrupt mask = 0: loss of signal interrupt enabled = 1: loss of signal interrupt masked
46 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-47 intm1: interrupt mask register 1 (r/w, address = 12h,52h,92h,d2h) symbol bit default description dac_ov_im 7 1 dac arithmetic overflow interrupt mask = 0: dac arithmetic overflow interrupt enabled = 1: dac arithmetic overflow interrupt masked jaov_im 6 1 ja overflow interrupt mask = 0: ja overflow interrupt enabled = 1: ja overflow interrupt masked jaud_im 5 1 ja underflow interrupt mask = 0: ja underflow interrupt enabled = 1: ja underflow interrupt masked err_im 4 1 prbs/qrss logic erro r detect interrupt mask = 0: prbs/qrss logic error detect interrupt enabled = 1: prbs/qrss logic error detect interrupt masked exz_im 3 1 receive excess zeros interrupt mask = 0: receive excess zeros interrupt enabled = 1: receive excess zeros interrupt masked cv_im 2 1 receive error interrupt mask = 0: receive error interrupt enabled = 1: receive error interrupt masked timer_im 1 1 one-second timer expiration interrupt mask = 0: one-second timer expiration interrupt enabled = 1: one-second timer expiration interrupt masked cnt_im 0 1 counter overflow interrupt mask = 0: counter overflow interrupt enabled = 1: counter overflow interrupt masked
47 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-48 intes: interrupt trigger edges select register (r/w, address = 13h, 53h,93h,d3h) symbol bit default description eq_ies 7 0 this bit determines the equalizer out of range interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the eq_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the eq_s bit in the stat0 status register. iblba_ies 6 0 this bit determines the inband loopback activate code interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the iblba_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the iblba_s bit in the stat0 status register. iblbd_ies 5 0 this bit determines the inband loopback deactivate code interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the iblbd_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the iblbd_s bit in the stat0 status register. prbs_ies 4 0 this bit determines the prbs/qrss synchronization status interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the prbs_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the prbs_s bit in the stat0 status register. tclk_ies 3 0 this bit determines the tclk loss interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the tclk_los bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the tclk_los bit in the stat0 status register. df_ies 2 0 this bit determines the driver failure interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the df_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the df_s bit in the stat0 status register. ais_ies 1 0 this bit determines the ais interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the ais_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the ais_s bit in the stat0 status register. los_ies 0 0 this bit determines the los interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the los_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the los_s bit in the stat0 status register.
48 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 4.2.7 line status registers table-49 stat0: line status register 0 (real time status monitor) (r, address = 14h,54h,94h,d4h) symbol bit default description eq_s 7 0 equalizer status indication = 0: in range = 1: out of range iblba_s 6 0 inband loopback activate code receive status indication = 0: no inband loopback activate code is detected = 1: activate code has been detected for more than t ms. even there is bit error, this bit remains set as long as the bit error rate is less than 10 -2 . note1: automatic remote loopback switching is disabled (arlp = 0), t = 40 ms. if automatic remote loopback switching is enabled (arlp = 1), t = 5.1 s. the rising edge of this bit activates the remote loopback operation in local end. note2: if iblba_im=0 and iblba_ies=0, a ?0? to ?1? transition on this bit will cause an activate code detect interrupt. if iblba_im=0 and iblba_ies=1, any changes on this bit will cause an activate code detect interrupt. iblbd_s 5 0 inband loopback deactivate code receive status indication = 0: no inband loopback deactivate code is detected = 1: the inband loopback deactivate code has been detected for more than t. even there is a bit error, this bit remains set as long as the bit error rate is less than 10 -2 . note1: automatic remote loopback switching is disabled (arlp = 0), t = 40 ms.if automatic remote loopback switching is enabled (arlp = 1), t= 5.1 s. the rising edge of this bit disables the remote loopback operation. note2: if iblbd_im=0 and iblbd_ies=0, a ?0? to ?1? transition on this bit will cause a deactivate code detect interrupt. if iblbd_im=0 and iblbd_ies=1, any changes on this bit will cause a deactivate code detect interrupt. prbs_s 4 0 synchronous status indica tion of prbs/qrss (real time) = 0: 2 15 -1 (e1) prbs or 2 20 -1 (t1/j1) qrss is not detected = 1: 2 15 -1 (e1) prbs or 2 20 -1 (t1/j1) qrss is detected. note: if prbs_im=0 and prbs_ies=0, a ?0? to ?1? transition on this bit will cause a synchronous status detect interrupt. if prbs_im=0 and prbs_ies=1, any changes on this bit will cause a synchronous status detect interrupt. tclk_los 3 0 tclkn loss indication = 0: normal = 1: tclkn pin has not toggled for more than 70 mclk cycles. note: if tclk_im=0 and tclk_ies=0, a ?0? to ?1? transition on this bit will cause an interrupt. if tclk_im=0 and tclk_ies=1, any changes on this bit will cause an interrupt.
49 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit df_s 2 0 line driver status indication = 0: normal operation = 1: line driver short circuit is detected. note: if df_im=0 and df_ies=0, a ?0? to ?1? transition on this bit will cause an interrupt. if df_im=0 and df_ies=1, any changes on this bit will cause an interrupt. ais_s 1 0 alarm indication signal status detection = 0: no ais signal is detected in the receive path = 1: ais signal is detected in the receive path note: if ais_im=0 and ais_ies=0, a ?0? to ?1? transition on this bit will cause an interrupt. if ais_im=0 and ais_ies=1, any changes on this bit will cause an interrupt. los_s 0 0 loss of signal status detection = 0: loss of signal on rtip/rring is not detected = 1: loss of signal on rtip/rring is detected note: if los_im=0 and los_ies=0, a ?0? to ?1? transition on this bit will cause an interrupt. if los_im=0 and los_ies=1, any changes on this bit will cause an interrupt. table-49 stat0: line status register 0 (real time status monitor) (continued) (r, address = 14h,54h,94h,d4h) symbol bit default description
50 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-50 stat1: line status register 1 (real time status monitor) (r, address = 15h, 55h,95h, d5h) symbol bit default description - 7-6 00 reserved rlp_s 5 0 indicating the status of remote loopback = 0: the remote loopback is inactive. = 1: the remote loopback is active (closed). latt[4:0] 4-0 00000 line attenuation indication in db relative to a 3 v peak pulse level 00000 0 to 2 db 00001 2 to 4 db 00010 4 to 6 db 00011 6 to 8 db 00100 8 to 10 db 00101 10 to 12 db 00110 12 to 14 db 00111 14 to 16 db 01000 16 to 18 db 01001 18 to 20 db 01010 20 to 22 db 01011 22 to 24 db 01100 24 to 26 db 01101 26 to 28 db 01110 28 to 30 db 01111 30 to 32 db 10000 32 to 34 db 10001 34 to 36 db 10010 36 to 38 db 10011 38 to 40 db 10100 40 to 42 db 10101 42 to 44 db 10110-11111 >44 db
51 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 4.2.8 interrupt status registers table-51 ints0: interrupt status register 0 (this register is reset after a read o peration) (r, address = 16h, 56h,96h, d6h) symbol bit default description eq_is 7 0 this bit indicates the occurrence of equalizer out of range interrupt event. = 0: no interrupt event from the equalizer out of range occurred = 1: interrupt event from the equalizer out of range occurred iblba_is 6 0 this bit indicates the occurrence of the inband loopback activate code interrupt event. = 0: no inband loopback activate code interrupt event occurred = 1: inband loopback activate code interrupt event occurred iblbd_is 5 0 this bit indicates the occurrence of the inband loopback deactivate code interrupt event. = 0: no inband loopback deactivate code interrupt event occurred = 1: interrupt event of the received inband loopback deactivate code occurred. prbs_is 4 0 this bit indicates the occurrence of the interrupt event generated by the prbs/qrss synchronization status. = 0: no prbs/qrss synchronization status interrupt event occurred = 1: prbs/qrss synchronization status interrupt event occurred tclk_los_is 3 0 this bit indicates the occurrence of the interrupt event generated by the tclkn loss detection. = 0: no tclkn loss interrupt event. = 1:tclkn loss interrupt event occurred. df_is 2 0 this bit indicates the occurrence of the interrupt event generated by the driver failure. = 0: no driver failure interrupt event occurred = 1: driver failure interrupt event occurred ais_is 1 0 this bit indicates the occurrence of the ais (alarm indication signal) interrupt event. = 0: no ais interrupt event occurred = 1: ais interrupt event occurred los_is 0 0 this bit indicates the occurrence of the los (loss of signal) interrupt event. = 0: no los interrupt event occurred = 1: los interrupt event occurred
52 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 4.2.9 counter registers table-52 ints1: interrupt status register 1 (this register is reset and relevant interrupt request is cleared after a read) (r, address = 17h, 57h,97h, d7h) symbol bit default description dac_ov_is 7 0 this bit indicates the occurrence of the pulse amplit ude overflow of arbitrary waveform generator interrupt event. = 0: no pulse amplitude overflow of arbitrary waveform generator interrupt event occurred = 1: the pulse amplitude overflow of arbitrary waveform generator interrupt event occurred jaov_is 6 0 this bit indicates the occurrence of the jitter attenuator overflow interrupt event. = 0: no ja overflow interrupt event occurred = 1: a overflow interrupt event occurred jaud_is 5 0 this bit indicates the occurrence of the jitter attenuator underflow interrupt event. = 0: no ja underflow interrupt event occurred = 1: ja underflow interrupt event occurred err_is 4 0 this bit indicates the occurrence of the interrupt event generated by the detected prbs/qrss logic error. = 0: no prbs/qrss logic error interrupt event occurred = 1: prbs/qrss logic error interrupt event occurred exz_is 3 0 this bit indicates the occurrence of the excessive zeros interrupt event. = 0: no excessive zeros interrupt event occurred = 1: exz interrupt event occurred cv_is 2 0 this bit indicates the occurrence of the code violation interrupt event. = 0: no code violation interrupt event occurred = 1: code violation interrupt event occurred tmov_is 1 0 this bit indicates the occurrence of the one-second timer expiration interrupt event. = 0: no one-second timer expiration interrupt event occurred = 1: one-second timer expiration interrupt event occurred cnt_ov_is 0 0 this bit indicates the occurrence of the counter overflow interrupt event. = 0: no counter overflow interrupt event occurred = 1: counter overflow interrupt event occurred table-53 cnt0: error counter l-byte register 0 (r, address = 18h, 58h,98h, d8h) symbol bit default description cnt_l[7:0] 7-0 00h this register contains the lower eight bits of the 16-bit error counter. cnt_l[0] is the lsb. table-54 cnt1: error counter h-byte register 1 (r, address = 19h, 59h,99h,d9h) symbol bit default description cnt_h[7:0] 7-0 00h this register contains the upper eight bits of the 16-bit error counter. cnt_h[7] is the msb.
53 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 4.2.10 transmit and receive termination register table-55 term: transmit and receive termination configuration register (r/w, address = 1ah, 5ah,9ah,dah) symbol bit default description - 7-6 00 reserved t_term[2:0] 5-3 000 these bits select the internal termination for transmit line impedance matching. = 000: internal 75 ? impedance matching = 001: internal 120 ? impedance matching = 010: internal 100 ? impedance matching = 011: internal 110 ? impedance matching =1xx: selects external impedance matching resistors for e1 mode only. t1/j1 does not require external imped- ance resistors (see table-14 ). r_term[2:0] 2-0 000 these bits select the internal termination for receive line impedance matching. = 000: internal 75 ? impedance matching = 001: internal 120 ? impedance matching = 010: internal 100 ? impedance matching = 011: internal 110 ? impedance matching = 1xx: selects external impedance matching resistors (see table-15 ).
54 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 5 ieee std 1149.1 jtag test access port the idt82v2084 supports the digital boundary scan specification as described in the ieee 1149.1 standards. the boundary scan architecture consis ts of data and instruction regis- ters plus a test access port (tap) controller. control of the tap is per- formed through signals applied to the test mode select (tms) and test clock (tck) pins. data is shifted into the registers via the test data input (tdi) pin, and shifted out of the registers via the test data output (tdo) pin. both tdi and tdo are clocked at a rate determined by tck. the jtag boundary scan register s include bsr (boundary scan reg- ister), idr (device identification r egister), br (bypass register) and ir (instruction register). these will be described in the following pages. refer to for architecture. figure-21 jtag architecture bsr (boundary scan register) idr (device identification register) br (bypass register) ir (instruction register) mux tdo tdi tck tms trst control<6:0> mux select high impedance enable tap (test access port) controller parallel latched output digital output pins digital input pins
55 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 5.1 jtag instructions and instruction reg- ister the ir (instruction register) with instruction decode block is used to select the test to be executed or t he data register to be accessed or both. the instructions are shifted in lsb first to this 3-bit register. see table- 56 for details of the codes and the instructions related. 5.2 jtag data register 5.2.1 device identification register (idr) the idr can be set to define the producer number, part number and the device revision, which can be used to verify the proper version or re- vision number that has been used in the system under test. the idr is 32 bits long and is partitioned as in table-57 . data from the idr is shifted out to tdo lsb first. 5.2.2 bypass register (br) the br consists of a single bit. it can provide a serial path between the tdi input and tdo output, bypassing the bsr to reduce test access times. 5.2.3 boundary scan register (bsr) the bsr can apply and read test patterns in parallel to or from all the digital i/o pins. the bsr is a 98 bits long shift register and is initialized and read using the instruction extest or sample/preload. each pin is related to one or more bits in the bsr. for details, please refer to the bsdl file. table-56 instruction register description ir code instruction comments 000 extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is placed between tdi and tdo. the signal on the input pins can be sam- pled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. the signal on the output pins can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. 100 sample / preload the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan re gister is placed between tdi and tdo. the normal path between idt82v2084 lo gic and the i/o pins is maintained. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. 110 idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identi fication code can then be shifted out using the shift-dr state. 111 bypass the bypass instruction shifts data from input tdi to output tdo with one tck clock period delay. the instruction is us ed to bypass the device. table-57 device identifica tion register description bit no. comments 0 set to ?1? 1-11 producer number 12-27 part number 28-31 device revision
56 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 5.2.4 test access port controller the tap controller is a 16-st ate synchronous state machine. figure-22 shows its state diagram following the description of each state. note that the figure contains two main branches to access either the data or instruc- tion registers. the value shown next to each state transition in this figure states the value present at tms at each rising edge of tck. please refer to table-58 for details of the state description. table-58 tap controller state description state description test logic reset in this state, the test logic is disabled. the device is set to normal operation. during initialization, the de vice initializes the instruction register with the idcode instruction. regardless of the original state of the controller, the controller enters the test-logic-reset sta te when the tms input is held high for at least 5 rising edges of tck. the controller remains in this state while tms is high. the device p rocessor auto- matically enters this state at power-up. run-test/idle this is a controller state between scan operations. once in this state, the controller remains in the state as lon g as tms is held low. the instruction register and all test data registers retain their previous state. when tms is high and a rising edge is applied to tck, the control- ler moves to the select-dr state. select-dr-scan this is a temporary controller state and the instruction does not change in this state. the test data register se lected by the current instruc- tion retains its previous state. if tms is held low and a rising edge is applied to tck when in this state, the controller move s into the cap- ture-dr state and a scan sequence for the selected test data register is initiated. if tms is held high and a rising edge appli ed to tck, the controller moves to the select-ir-scan state. capture-dr in this state, the boundary scan register captures input pin data if the current inst ruction is extest or sample/prel oad. the instruc- tion does not change in this state. the other test data registers, which do not have parallel input, are not changed. when the tap controller is in this state and a rising edge is applied to tck, the controller enters the exit1-dr state if tms is high or the shift-dr s tate if tms is low. shift-dr in this controller state, the test data register connected between tdi and tdo as a result of the current instruction s hifts data on stage toward its serial output on each rising edge of tck. the instruction does not change in this state. when the tap controller is in this state and a rising edge is applied to tck, the controller enters the exit1-dr state if tms is high or remains in the shift-dr state i f tms is low. exit1-dr this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update-dr state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the pause-dr state. the test data register selected by the current instruction retains its previous value and the instruction does not chang e during this state. pause-dr the pause state allows the test controller to temporarily halt the shifting of data through the test data register in t he serial path between tdi and tdo. for example, this state could be used to allow the tester to reload its pin memory from disk during application of a l ong test sequence. the test data register selected by the current instruction retains its previous value and the instruction does not ch ange during this state. the controller remains in this state as long as tms is low. when tms goes high and a rising edge is applied to tck, the controller moves to the exit2-dr state. exit2-dr this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update-dr state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the shift-dr state. the test data register selected by the current instruction retains its previous value and the instruction does not chang e during this state. update-dr the boundary scan register is provided with a latched parallel output to prevent changes while data is shifted in resp onse to the extest and sample/preload instructions. when the tap controller is in this state and the boundary scan register is selected, data is l atched into the parallel output of this register from the shift-register path on the falling edge of tck. the data held at the latched parallel output changes only in this state. all shift-register stages in the test data register selected by the current instruction retain thei r previous value and the instruction does not change during this state. select-ir-scan this is a temporary controller state. the test data register selected by the current instruction retains its prev ious state. if tms is held low and a rising edge is applied to tck when in this state, the controller moves into the capture-ir state, and a scan sequence for the instruc- tion register is initiated. if tms is held high and a rising edge is applied to tck, the controller moves to the test-logic-res et state. the instruction does not change during this state. capture-ir in this controller state, the shift register contained in the instruction register loads a fixed value of '100' on th e rising edge of tck. this sup- ports fault-isolation of the board-level serial test data path. data registers selected by the current instruction retain their value and the instruction does not change during this state. when the controller is in this state and a rising edge is applied to tck, the co ntroller enters the exit1-ir state if tms is held high, or the shift-ir state if tms is held low. shift-ir in this state, the shift register contained in the instruction register is connected between tdi and tdo and shifts dat a one stage towards its serial output on each rising edge of tck. the test data register selected by the current instruction retains its previous value and the instruc- tion does not change during this state. when the controller is in this state and a rising edge is applied to tck, the controlle r enters the exit1- ir state if tms is held high, or remains in the shift-ir state if tms is held low. exit1-ir this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update-ir state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the pause-ir state. the test data register selected by the current instruction retains its previous value and the instruction does not chang e during this state.
57 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit figure-22 jtag state diagram pause-ir the pause state allows the test controller to temporarily halt the shifting of data through the instruction register. t he test data register selected by the current instruction retains its previous value and the instruction does not change during this state. the contr oller remains in this state as long as tms is low. when tms goes high and a rising edge is applied to tck, the controller moves to the exit2-ir state. exit2-ir this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update-ir state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the shift-ir state. the test data register selected by the current instruction retains its previous value and the instruction does not change durin g this state. update-ir the instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of tck. when the new instruction has been latched, it becomes the current instruction. the test data registers selected by the current instruction retain their previous value. table-58 tap controller state description (continued) state description test-logic reset run test/idle select-dr select-ir capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 0 1 1 1 00 00 0 0 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1
58 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 6 test specifications 1.reference to ground 2.human body model 3.charge device model 4.constant input current 1.power consumption includes power consumption on device and load. digital levels are 10% of the supply rails and digital outpu ts driving a 50 pf capacitive load. 2.maximum power consumption over the full oper ating temperature and power supply voltage range. 3.in short haul mode, if internal impedance matching is chosen, e1 75 ? power dissipation values are measured with template puls[3:0] = 0000; e1 120 ? power dissipation values are measured with template puls[3:0] = 0001; t1 power dissipation values are measured with template puls[3:0] = 0110; j1 power dissipation values are mea- sured with template puls[3:0] = 0111. table-59 absolute maximum rating symbol parameter min max unit vdda, vddd core power supply -0.5 4.6 v vddio i/o power supply -0.5 4.6 v vddt1-4 transmit power supply -0.5 4.6 v vddr1-4 receive power supply -0.5 4.6 vin input voltage, any digital pin gnd-0.5 5.5 v input voltage, any rtip and rring pin 1 gnd-0.5 vddr+0.5 v esd voltage, any pin 2000 2 v 500 3 v iin transient latch-up current, any pin 100 ma input current, any digital pin 4 -10 10 ma dc input current, any analog pin 4 100 ma pd maximum power dissipation in package 1.69 w tc case temperature 120 c ts storage temperature -65 +150 c caution exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to abso lute maximum rating conditions for extended periods may affect device reliability. table-60 recommended operation conditions symbol parameter min typ max unit vdda,vddd core power supply 3.13 3.3 3.47 v vddio i/o power supply 3.13 3.3 3.47 v vddt transmitter power supply 3.13 3.3 3.47 v vddr receive power supply 3.13 3.3 3.47 v ta ambient operating temperature -40 25 85 c total current dissipation 1,2,3 e1, 75 ? load 50% ones density data 100% ones density data - - 250 300 270 320 ma e1, 120 ? load 50% ones density data 100% ones density data - - 240 280 260 300 ma t1, 100 ? load 50% ones density data 100% ones density data - - 270 360 290 380 ma j1, 110 ? load 50% ones density data 100% ones density data - - 230 300 250 320 ma
59 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 1.maximum power and current consumption over the full operating temperature and power supply voltage range. includes all channe ls. 2.power consumption includes power absorbed by line load and external transmitter components. 3.t1 is measured with maximum cable length. table-61 power consumption symbol parameter min typ max 1,2 unit e1, 3.3 v, 75 ? load 50% ones density data: 100% ones density data: - - 830 990 - 1110 mw e1, 3.3 v, 120 ? load 50% ones density data: 100% ones density data: - - 790 920 - 1050 mw t1, 3.3 v, 100 ? load 3 50% ones density data: 100% ones density data: - - 890 1190 - 1320 mw j1, 3.3 v, 110 ? load 50% ones density data: 100% ones density data: - - 760 990 1110 mw table-62 dc characteristics symbol parameter min typ max unit v il input low level voltage - - 0.8 v v ih input high voltage 2.0 - - v v ol output low level voltage (iout=1.6ma) - - 0.4 v v oh output high level voltage (iout=400 a) 2.4 - vddio v v ma analog input quiescent voltage (rtip, rring pin while floating) 1.5 v i i input leakage current tms, tdi, trst all other digital input pins -10 50 10 a a i zl high impedance leakage current -10 10 a ci input capacitance 15 pf co output load capacitance 50 pf co output load capacitance (bus pins) 100 pf
60 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-63 e1 receiver electrical characteristics symbol parameter min typ max unit test conditions receiver sensitivity short haul with cable loss@1024khz: long haul with cable loss@1024khz: -10 -43 db analog los level short haul long haul -4 800 -48 mvp-p db a los level is programmable for long haul allowable consecutive zeros before los g.775: i.431/etsi300233: 32 2048 los reset 12.5 % ones g.775, etsi 300 233 receive intrinsic jitter 20hz - 100khz 0.05 u.i. ja enabled input jitter tolerance 1 hz ? 20 hz 20 hz ? 2.4 khz 18 khz ? 100 khz 37 5 2 u.i. u.i. u.i. g.823, with 6 db cable attenuation zdm receiver differential input impedance 20 k ? internal mode input termination resistor tolerance 1% rrx receive return loss 51 khz ? 102 khz 102 khz - 2.048 mhz 2.048 mhz ? 3.072 mhz 20 20 20 db db db g.703 internal termination rpd receive path delay single rail dual rail 7 2 u.i. u.i. ja disabled
61 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-64 t1/j1 receiver electrical characteristics symbol parameter min typ max unit test conditions receiver sensitivity short haul with cable loss@772khz: long haul with cable loss@772khz: -10 -36 db analog los level short haul long haul -4 800 -48 mvp-p db a los level is programmable for long haul allowable consecutive zeros before los t1.231-1993 i.431 175 1544 los reset 12.5 % ones g.775, etsi 300 233 receive intrinsic jitter 10 hz ? 8 khz 10 hz ? 40 khz 8 khz ? 40 khz wide band 0.02 0.025 0.025 0.050 u.i. u.i. u.i. u.i. ja enabled ( in receive path) input jitter tolerance 0.1 hz ? 1 hz 4.9 hz ? 300 hz 10 khz ? 100 khz 138.0 28.0 0.4 u.i. u.i. u.i. at&t62411 zdm receiver differential input impedance 20 k ? internal mode input termination resistor tolerance 1% rrx receive return loss 39 khz ? 77 khz 77 khz - 1.544 mhz 1.544 mhz ? 2.316 mhz 20 20 20 db db db g.703 internal termination rpd receive path delay single rail dual rail 7 2 u.i. u.i. ja disabled
62 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-65 e1 transmitter electrical characteristics symbol parameter min typ max unit vo-p output pulse amplitudes e1, 75 ? load e1, 120 ? load 2.14 2.7 2.37 3.0 2.60 3.3 v v vo-s zero (space) level e1, 75 ? load e1, 120 ? load -0.237 -0.3 0.237 0.3 v v transmit amplitude variation with supply -1 +1 % difference between pulse sequences for 17 consecutive pulses (t1.102) 200 mv tpw output pulse width at 50% of nominal amplitude 232 244 256 ns ratio of the amplitudes of positive and negative pulses at the center of the pulse interval (g.703) 0.95 1.05 ratio of the width of positive and negative pulses at the center of the pulse interval (g.703) 0.95 1.05 rtx transmit return loss (g.703) 51 khz ? 102 khz 102 khz - 2.048 mhz 2.048 mhz ? 3.072 mhz 20 15 12 db db db jtxp-p intrinsic transmit jitter (tclk is jitter free) 20 hz ? 100 khz 0.050 u.i. td transmit path delay (ja is disabled) single rail dual rail 8.5 4.5 u.i. u.i. isc line short circuit current 100 ma
63 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-66 t1/j1 transmitter electrical characteristics symbol parameter min typ max unit vo-p output pulse amplitudes 2.4 3.0 3.6 v vo-s zero (space) level -0.15 0.15 v transmit amplitude variation with supply -1 +1 % difference between pulse sequences for 17 consecutive pulses(t1.102) 200 mv tpw output pulse width at 50% of nominal amplitude 338 350 362 ns pulse width variation at the half amplitude (t1.102) 20 ns imbalance between positive and negative pulses amplitude (t1.102) 0.95 1.05 output power level (t1.102) @772khz @1544khz (referenced to power at 772khz) 12.6 -29 17.9 dbm dbm rtx transmit return loss 39 khz ? 77 khz 77 khz ? 1.544 mhz 1.544 mhz ? 2.316 mhz 20 15 12 db db db jtxp-p intrinsic transmit jitter (tclk is jitter free) 10 hz ? 8 khz 8 khz ? 40 khz 10 hz ? 40 khz wide band 0.020 0.025 0.025 0.050 u.i.p-p u.i.p-p u.i.p-p u.i.p-p td transmit path delay (ja is disabled) single rail dual rail 8.5 4.5 u.i. u.i. i sc line short circuit current 100 ma
64 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 1.relative to nominal frequency, mclk= 100 ppm 2.rclk duty cycle widths will vary depending on extent of received pulse jitter displacement. maximum and minimum rclk duty cyc les are for worst case jitter conditions (0.2ui displacement for e1 per itu g.823). 3.for all digital outputs. c load = 15pf table-67 transmitter and receiver timing characteristics symbol parameter min typ max unit mclk frequency e1: t1/j1: 2.048/49.152 1.544/37.056 mhz mclk tolerance -100 100 ppm mclk duty cycle 30 70 % transmit path tclk frequency e1: t1/j1: 2.048 1.544 mhz tclk tolerance -50 +50 ppm tclk duty cycle 10 90 % t1 transmit data setup time 40 ns t2 transmit data hold time 40 ns delay time of thz low to driver high impedance 10 us delay time of tclk low to driver high impedance 75 u.i. receive path clock recovery capture range 1 e1 80 ppm t1/j1 180 rclk duty cycle 2 40 50 60 % t4 rclk pulse width 2 e1: t1/j1: 457 607 488 648 519 689 ns t5 rclk pulse width low time e1: t1/j1: 203 259 244 324 285 389 ns t6 rclk pulse width high time e1: t1/j1: 203 259 244 324 285 389 ns rise/fall time 3 20 ns t7 receive data setup time e1: t1/j1: 200 200 244 324 ns t8 receive data hold time e1: t1/j1: 200 200 244 324 ns
65 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit figure-23 transmit system interface timing figure-24 receive system interface timing table-68 jitter tolerance jitter tolerance min typ max unit standard e1: 1 hz 20 hz ? 2.4 khz 18 khz ? 100 khz 37 1.5 0.2 u.i. u.i. u.i. g.823 cable attenuation is 6db t1/j1: 1 hz 4.9 hz ? 300 hz 10 khz ? 100 khz 138.0 28.0 0.4 u.i. u.i. u.i. at&t 62411 tdnn tdn/tdpn tclkn t1 t2 rdnn/cvn rdpn/rdn rclkn t4 t7 t6 t7 t5 t8 t8 (rclk_sel = 1) (rclk_sel = 0) rdpn/rdn rdnn/cvn
66 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit figure-25 e1 jitter tolerance performance figure-26 t1/j1 jitter tolerance performance
67 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit table-69 jitter attenuator characteristics parameter min typ max unit jitter transfer function corner (-3db) frequency e1, 32/64/128 bits fifo jabw = 0: jabw = 1: t1/j1, 32/64/128 bits fifo jabw = 0: jabw = 1: 6.8 0.9 5 1.25 hz hz hz hz jitter attenuator e1: (g.736) @ 3 hz @ 40 hz @ 400 hz @ 100 khz t1/j1: (per at&t pub.62411) @ 1 hz @ 20 hz @ 1 khz @ 1.4 khz @ 70 khz -0.5 -0.5 +19.5 +19.5 db 0 0 +33.3 40 40 jitter attenuator latency delay 32 bits fifo: 64 bits fifo: 128 bits fifo: 16 32 64 u.i. u.i. u.i. input jitter tolerance before fifo overflow or underflow 32 bits fifo: 64 bits fifo: 128 bits fifo: 28 58 120 u.i. u.i. u.i.
68 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit figure-27 e1 jitter transfer performance figure-28 t1/j1 jitter transfer performance
69 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit figure-29 jtag interface timing table-70 jtag timing characteristics symbol parameter min typ max unit t1 tck period 100 ns t2 tms to tck setup time tdi to tck setup time 25 ns t3 tck to tms hold time tck to tdi hold time 25 ns t4 tck to tdo delay time 50 ns tck t1 t2 t3 tdo tms tdi t4
70 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 7 microcontroller interface timing characteristics 7.1 serial interface timing figure-30 serial interface write timing figure-31 serial interface read timing with sclke=1 figure-32 serial interface read timing with sclke=0 table-71 serial interface timing characteristics symbol parameter min typ max unit comments t1 sclk high time 82 ns t2 sclk low time 82 ns t3 active cs to sclk setup time 5 ns t4 last sclk hold time to inactive cs time 41 ns t5 cs idle time 41 ns t6 sdi to sclk setup time 0 ns t7 sclk to sdi hold time 62 ns t10 sclk to sdo valid delay time 75 ns t11 inactive cs to sdo high impedance hold time 70 ns msb lsb lsb cs sclk sdi t1 t2 t3 t4 t5 t6 t7 t7 1 2 3 4 5 15 16 17 18 19 20 21 22 23 24 sdo cs sclk t4 t11 t10 7 6 5 4 3 2 1 0 1 2 3 4 5 15 161718192021222324 sdo cs sclk t4 t11 t10 7 6 5 4 3 2 1 0
71 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit 7.2 parallel interface timing figure-33 non_multiple xed motorola read timing table-72 non_multiplexed motoro la read timing characteristics symbol parameter min max unit trc read cycle time 190 ns tdw valid ds width 180 ns trwv delay from ds to valid read signal 15 ns trwh r/ w to ds hold time 65 ns tav delay from ds to valid address 15 ns tadh address to ds hold time 65 ns tprd ds to valid read data propagation delay 175 ns tdaz delay from ds inactive to data bus high impedance 5 20 ns trecovery recovery time from read cycle 5 ns a[x:0] valid address ds + cs r/ w read d[7:0] trwv valid data tdaz tadh trwh tprd trc tdw tav trecovery
72 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit figure-34 non_multiplexed motorola write timing table-73 non_multiplexed motorola write timing characteristics symbol parameter min max unit twc write cycle time 120 ns tdw valid ds width 100 ns trwv delay from ds to valid write signal 15 ns trwh r/ w to ds hold time 65 ns tav delay from ds to valid address 15 ns tah address to ds hold time 65 ns tdv delay from ds to valid write data 15 ns tdhw write data to ds hold time 65 ns trecovery recovery time from write cycle 5 ns a[x:0] valid address ds + cs r/ w write d[7:0] trwv tdhw tah trwh twc tdw tav valid data tdv trecovery
73 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit figure-35 non_multiplexed intel read timing table-74 non_multiplexed intel read timing characteristics symbol parameter min max unit trc read cycle time 190 ns trdw valid rd width 180 ns tav delay from rd to valid address 15 ns tah address to rd hold time 65 ns tprd rd to valid read data propagation delay 175 ns tdaz delay from rd inactive to data bus high impedance 5 20 ns trecovery recovery time from read cycle 5 ns a[x:0] valid address cs + rd read d[7:0] valid data tdaz tah tprd trdw tav note: wr should be tied to high trecovery trc
74 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit figure-36 non_multiplexed intel write timing table-75 non_multiplexed intel write timing characteristics symbol parameter min max unit twc write cycle time 120 ns twrw valid wr width 100 ns tav delay from wr to valid address 15 ns tah address to wr hold time 65 ns tdv delay from wr to valid write data 15 ns tdhw write data to wr hold time 65 ns trecovery recovery time from write cycle 5 ns a[x:0] valid address wr + cs write d[7:0] tdhw tah twc twrw tav valid data tdv note: rd should be tied to high trecovery
75 industrial temperature ranges quad channel t1/e1/j1 long haul/sho rt haul line interface unit corporate headquarters 2975 stender way santa clara, ca 95054 for sales: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* for tech support : 408-330-1753 email:telecomhelp@idt.com to search for sales office near you, please click the sales bu tton found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. ordering information datasheet document history 06/26/2003 pgs. 16, 17, 28, 29, 33, 41, 59, 60. 08/22/2003 pgs. 17, 18. 07/19/2004 pgs. 30, 62, 63 idt xxxxxxx xx x device type blank process/ temperature range pf 82v2084 industrial (-40 c to +85 c) thin quad flatpack (tqfp, pk128) long haul/short haul liu
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